IP Library Granted Patent US 6,949,816
Granted Patent B2
US 6,949,816 · App. 10/420,054 · Granted Sep 27, 2005

Semiconductor component having first surface area for electrically coupling to a semiconductor chip and second surface area for electrically coupling to a substrate, and method of manufacturing same

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Quick Facts
Patent No.
US 6,949,816
App. No.
10/420,054
Granted
Sep 27, 2005
Kind
B2
Abstract

A semiconductor component for electrical coupling to a substrate ( 230 ) includes: a semiconductor chip ( 110 ); a non-leaded leadframe ( 120 ) including a plurality of electrical contacts ( 130 ) located around a periphery ( 111 ) of the semiconductor chip; a first electrical conductor ( 140 ) electrically coupling together the semiconductor chip and the non-leaded leadframe; and a mold compound ( 210 ) disposed around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts includes: a first surface ( 310 ) having a first surface area for electrically coupling to the semiconductor chip; and a second surface ( 320 ) opposite the first surface and having a second surface area for electrically coupling to the substrate, where the second surface area is larger than the first surface area.

Claims (106)

1. A semiconductor component for electrical coupling to a substrate, the semiconductor component comprising:

a semiconductor chip;

a non-leaded leadframe comprising a plurality of electrical contacts located around a periphery of the semiconductor chip;

a first electrical conductor electrically coupling together the semiconductor chip and the non-leaded leadframe; and

a mold compound disposed around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts,

wherein:

at least one electrical contact of the plurality of electrical contacts comprises:

a first surface having a first surface area for electrically coupling to the semiconductor chip;

a second surface opposite the first surface and having a second surface area for electrically coupling to the substrate; and

a side surface coupling together the first surface and the second surface;

the side surface has a first concave section and a second concave section adjacent to the first concave section; and

the second surface area is larger than the first surface area.

2. The semiconductor component of claim 1 wherein:

the at least one electrical contact comprises a trapezoidal cross-sectional shape.

3. The semiconductor component of claim 1 wherein:

the first concave section and the second concave section form at least one mold lock feature.

4. The semiconductor component of claim 1 wherein:

the first concave section is located between the first surface and the second concave section; and

the second concave section is located between the second surface and the first concave section.

5. The semiconductor component of claim 1 wherein:

the first concave section has a first radius of curvature; and

the second concave section has a second radius of curvature less than the first radius of curvature.

6. The semiconductor component of claim 1 wherein:

the at least one electrical contact further comprises:

a side surface coupling the first surface to the second surface and comprising at least one mold lock feature.

7. The semiconductor component of claim 1 wherein:

the first surface comprises at least one mold lock feature.

8. The semiconductor component of claim 7 wherein:

the at least one mold lock feature comprises a recess within the first surface.

9. The semiconductor component of claim 1 wherein:

the second surface has a substantially constant width.

10. The semiconductor component of claim 1 wherein:

the second surface has a first section having a first width and a second section having a second width; and

the second width is less than the first width.

11. The semiconductor component of claim 1 wherein:

the first surface has a first length and a first width;

the second surface has the first length and a second width; and

the second width is greater than the first width.

12. The semiconductor component of claim 1 wherein:

the non-leaded leadframe has a thickness of at least 0.5 centimeters.

13. The semiconductor component of claim 1 wherein:

the second surface of the at least one electrical contact has a first section having a first width and a second section having a second width;

the second width is less than the first width; and

the second surface of another electrical contact of the plurality of electrical contacts has a substantially constant width substantially equal to the first width.

14. A semiconductor component for electrical coupling to a substrate, the semiconductor component comprising:

a semiconductor chip;

a non-leaded leadframe comprising a plurality of electrical contacts located around a periphery of the semiconductor chip; and

a mold compound disposed around the semiconductor chip and the plurality of electrical contacts;

wherein:

each electrical contact in the plurality of electrical contacts comprises:

a first surface having a first surface area for electrical coupling to the semiconductor chip;

a second surface opposite the first surface and having a second surface area for electrical coupling to the substrate; and

a side surface coupling together the first surface and the second surface;

the second surface area is larger than the first surface area;

each electrical contact of the plurality of electrical contacts comprises a trapezoidal cross-sectional shape;

each side surface comprises at least one mold lock feature; and

the at least one mold lock feature comprises:

a first mold lock feature comprising a first concave section in the side surface; and

a second mold lock feature comprising a second concave section in the side surface and adjacent to the first concave section.

15. The semiconductor component of claim 14 wherein:

the first concave section has a first radius of curvature; and

the second concave section has a second radius of curvature less than the first radius of curvature.

16. The semiconductor component of claim 14 wherein:

the first mold lock feature is located between the first surface and the second mold lock feature; and

the second mold lock feature is located between the second surface and the first mold lock feature.

17. The semiconductor component of claim 14 wherein:

the first surface comprises a first mold lock feature.

18. The semiconductor component of claim 17 wherein:

the first mold lock feature comprises a notch.

19. The semiconductor component of claim 17 wherein:

the first mold lock feature comprises a notch; and

the at least one mold lock feature comprises:

a second mold lock feature comprising a first concave section in the side surface; and

a third mold lock feature comprising a second concave section in the side surface and adjacent to the second mold lock feature.

20. The semiconductor component of claim 19 wherein:

the second mold lock feature is located between the first surface and the third mold lock feature; and

the third mold lock feature is located between the second surface and the second mold lock feature.

21. The semiconductor component of claim 17 wherein:

the second surface has a substantially constant width.

22. The semiconductor component of claim 17 wherein:

the second surface has a first section having a first width, a second section having a second width, and a third section coupling together the first section and the second section; and

the second width is less than the first width.

23. The semiconductor component of claim 22 wherein:

the first surface has a first length and the second width; and

the second surface has the first length.

24. The semiconductor component of claim 22 wherein:

the first surface has a first length and the second width; and

the second surface has a second length greater than the first length.

25. The semiconductor component of claim 24 wherein:

the second surface of a second one of the plurality of electrical contacts has a constant width substantially equal to the first width.

26. The semiconductor component of claim 14 wherein:

the non-leaded leadframe has a thickness of at least 0.5 centimeters.

27. A method of manufacturing a semiconductor component for electrical coupling to a substrate, the method comprising:

providing a non-leaded leadframe comprising:

a plurality of electrical contacts;

wherein:

each one of the plurality of electrical contacts comprises:

a first surface having a first surface area;

a second surface opposite the first surface and having a second surface area; and

a side surface coupling together the first surface and the second surface;

the side surface has a first concave section and a second concave section adjacent to the first concave section; and

the second surface area is larger than the first surface area;

mounting a semiconductor chip adjacent to the non-leaded leadframe;

coupling a first electrical conductor between the first surface of a first one of the plurality of electrical contacts and the semiconductor chip;

disposing a mold compound around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts; and

coupling a second electrical conductor between the second surface of the first one of the plurality of electrical contacts and the substrate.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2003
From: BROWN, CLEM H.; MOSNA, JR., FRANK J.; CHOW, WAI WONG
To: MOTOROLA, INC.
Reel/Frame 013991/0494 →