IP Library Granted Patent US 6,954,100
Granted Patent B2
US 6,954,100 · App. 10/660,847 · Granted Oct 11, 2005

Level shifter

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Quick Facts
Patent No.
US 6,954,100
App. No.
10/660,847
Granted
Oct 11, 2005
Kind
B2
Abstract

A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.

Claims (69)

1. An integrated circuit with a bi-directional level shifter, the bi-directional level shifter comprising:

a first signal terminal operable as an input and an output, wherein when being operable as an input, the first signal terminal receives a first signal compatible with a first voltage domain of the integrated circuit and wherein when being operable as an output, the first signal terminal provides a shifted signal compatible with the first voltage domain of the integrated circuit;

a second signal terminal operable as an output and an input, wherein when being operable as an output, the second signal terminal provides a shifted sign compatible with a second voltage domain of the integrated circuit and wherein when being operable as an input, the second signal terminal receives a second signal compatible with the second voltage domain of the integrated circuit; and

level shift circuitry coupled between the first signal terminal and the second signal terminal, the level shift circuitry translating the first signal compatible with the first voltage domain to the shifted signal compatible with the second voltage domain when the first signal terminal is operable as an input, the level shift circuitry translating the second signal compatible with the second voltage domain to the shifted signal compatible with the first voltage domain when the second signal terminal is operable as an input;

wherein the level shift circuitry further includes at least one current cut-off transistor, wherein responsive to being non conductive, the at least one current cut-off transistor operates to cut off current flowing in a current path between a first voltage domain voltage supply and second voltage domain voltage supply;

wherein the at least one current cut-off transistor includes a first cut-off transistor disposed within the first voltage domain and a second transistor disposed within the second voltage domain.

2. The integrated circuit of claim 1

wherein the level shifter has only one signal line that crosses a domain boundary between the first voltage domain and the second voltage domain.

3. The integrated circuit of claim 1 , wherein the level shift circuit is characterized as bidirectional level shift circuitry.

4. An integrated circuit with a bi-directional level shifter, the bi-directional level shifter comprising:

a first signal terminal operable as an input, wherein when being operable as an input, the first signal terminal receives a first signal compatible with a first voltage domain of the integrated circuit and wherein when being operable as an output, the first signal terminal provides a shifted signal compatible with the first voltage domain of the integrated circuit;

a second signal terminal operable as an output and an input, wherein when being operable as an output, the second signal terminal provides a shifted signal compatible with a second voltage domain of the integrated circuit and wherein when being operable as an input, the second signal terminal receives a second signal compatible with the second voltage domain of the integrated circuit; and

level shift circuitry coupled between the first signal terminal and the second signal terminal, the level shift circuitry translating the first signal compatible with the first voltage domain to the shifted signal compatible with the second voltage domain when the first signal terminal is operable as an input, the level shift circuitry translating the second signal compatible with the second voltage domain to the shifted signal compatible with the first voltage domain when the second signal terminal is operable as an input;

wherein the level shift circuitry further includes at least one current cut-off transistor, wherein responsive to being non conductive, the at least one current cut-off transistor operates to cut off current flowing in a current path between a first voltage domain voltage supply and second voltage domain voltage supply;

wherein the at least one current cut-off transistor includes first transistor and a second transistor, the first transistor being disposed within the first voltage domain and having a control terminal coupled to a first voltage domain voltage supply, and a current terminal, and the second transistor being disposed within the second voltage domain and having a control terminal coupled to a second voltage domain voltage supply and a current terminal coupled to the current terminal of the first transistor.

5. The integrated circuit of claim 4 , wherein the first transistor is characterized as in NFET and the second transistor is characterized as an NFET.

6. The integrated circuit of claim 4 , wherein the level shift circuitry is characterized as bidirectional level shift circuitry.

7. An integrated circuit with a bi-directional level shifter, the bi-directional level shifter comprising:

a first signal terminal operable as an input and an output, wherein when being operable as an input, the first signal terminal receives a first signal compatible with a first voltage domain of the integrated circuit and wherein when being operable as an output, the first signal terminal provides a shifted signal compatible with the first voltage domain of the integrated circuit;

a second signal terminal operable as an output and an input, wherein when being operable as an output, the second signal terminal provides a shifted signal compatible with a second voltage domain of the integrated circuit and wherein when being operable as an input, the second signal terminal receives a second signal compatible with the second voltage domain of the integrated circuit; and

level shift circuitry coupled between the first signal terminal and the second signal terminal, the level shift circuitry translating the first signal compatible with the first voltage domain to the shifted signal compatible with the second voltage domain when the first signal terminal is operable as an input, the level shift circuitry translating the second signal compatible with the second voltage domain to the shifted signal compatible with the first voltage domain when the second signal terminal is operable as an input;

wherein the level shift circuitry comprises:

a current path between the first signal terminal and the second signal terminal, the current path including a first transistor and a second transistor, the first transistor being disposed within the first voltage domain and having a first current terminal coupled to the first signal terminal, a control terminal coupled to a first voltage domain voltage supply, and a second current terminal, and the second transistor being disposed within the second voltage domain and having a first current terminal coupled to the second signal terminal, a control terminal coupled to a second voltage domain voltage supply, and a second current terminal coupled to the second current terminal of the first transistor.

8. The integrated circuit of claim 7 wherein the current path is the only current path of the level shift circuitry to cross a domain boundary between the first voltage domain and the second voltage domain.

9. The integrated circuit of claim 7 wherein the level shift circuitry further comprises:

a first transistor located in the first voltage domain and having a first current terminal coupled to the first voltage domain voltage supply and a second current terminal coupled to the current path;

a second transistor located in the first voltage domain and having a first current terminal coupled the first voltage domain voltage supply and a second current terminal coupled to a control terminal or the first transistor, and a control terminal coupled to the current path;

a third transistor located in the second voltage domain and having a first current terminal coupled to the second voltage domain voltage supply and a second current terminal coupled to the current path;

a fourth transistor located in the second voltage domain and having first current terminal coupled the second voltage domain voltage supply, a second current terminal coupled to the control terminal of the third transistor, and a control terminal coupled to the current path.

10. The integrated circuit of claim 7 , wherein the level shift circuitry is characterized as bidirectional level shift circuitry.

11. An integrated circuit with a bi-directional level shifter, the bi-directional level shifter comprising:

a first signal terminal operable as an input and an output, wherein when being operable as an input, the first signal terminal receives a first signal compatible with a first voltage domain of the integrated circuit and wherein when being operable as an output, the first signal terminal provides a shifted signal compatible with the first voltage domain of the integrated circuit;

a second signal terminal operable as an output and an input, wherein when being operable as an output, the second signal terminal provides a shifted sign compatible with a second voltage domain of the integrated circuit and wherein when being operable as an input, the second signal terminal receives a second signal compatible with the second voltage domain of the integrated circuit; and

level shift circuitry coupled between the first signal terminal and the second signal terminal, the level shift circuitry translating the first signal compatible with the first voltage domain to the shifted signal compatible with the second voltage domain when the first signal terminal is operable as an input, the level shift circuitry translating the second signal compatible with the second voltage domain to the shifted signal compatible with the first voltage domain when the second signal terminal is operable as an input;

wherein the integrated circuit further comprises:

a first circuit coupled to the first signal terminal, the first circuit including circuitry to enable the first circuit to receive the shifted signal from the first signal terminal and circuitry to enable the first circuit to provide the first signal to the first signal terminal;

a second circuit coupled to the second signal terminal, the second circuit including circuitry to enable the second circuit to receive the shifted signal from the second signal terminal and circuitry to enable the second circuit to provide the second signal to the second signal terminal.

12. The integrated circuit of claim 11 , wherein the level shift circuitry is characterized as bidirectional level shift circuitry.

13. An integrated circuit with a bi-directional level shifter, the bi-directional level shifter comprising:

a first signal terminal operable as an input and an output, wherein when being operable as an input, the first signal terminal receives a first signal compatible with a first voltage domain of the integrated circuit and wherein when being operable as an output, the first signal terminal provides a shifted signal compatible with the first voltage domain of the integrated circuit;

a second signal terminal operable as an output and an input, wherein when being operable as an output, the second signal terminal provides a shifted sign compatible with a second voltage domain of the integrated circuit and wherein when being operable as an input, the second signal terminal receives a second signal compatible with the second voltage domain of the integrated circuit; and

level shift circuitry coupled between the first signal terminal and the second signal terminal, the level shift circuitry translating the first signal compatible with the first voltage domain to the shifted signal compatible with the second voltage domain when the first signal terminal is operable as an input, the level shift circuitry translating the second signal compatible with the second voltage domain to the shifted signal compatible with the first voltage domain when the second signal terminal is operable as an input;

wherein the level shift circuitry further comprises:

a first transistor located in the first voltage domain and having a first current terminal coupled to a first voltage domain voltage supply and a second current terminal coupled to the first signal terminal;

a second transistor located in the first voltage domain and having a first current terminal coupled the first voltage domain voltage supply, a second current terminal coupled to the control terminal of the first transistor, and a control terminal coupled to the first signal terminal;

a third transistor located in the second voltage domain and having a first current terminal coupled to a second voltage domain voltage supply and a second current terminal coupled to the second signal terminal;

a fourth transistor located in the second voltage domain and having a first current terminal coupled the second voltage domain voltage supply, a second current terminal coupled to the control terminal of the third transistor, and a control terminal coupled to the second signal terminal.

14. The integrated circuit of claim 13 , wherein the level shift circuitry is characterized as bidirectional level shift circuitry.

15. A method comprising:

providing a first signal to a first signal terminal of a level shifter, the first signal compatible with a first voltage domain, wherein in response to the providing the first signal, the level shifter provides at a second signal terminal of the level shifter a shifted signal compatible with a second voltage domain; and

providing a second signal to the signal terminal of the level shifter, the second signal compatible with the second voltage domain, wherein in response to the providing the second signal, the level shifter provides at the first signal terminal a shifted signal compatible with a first voltage domain;

cutting off current of a current path of the level shifter between a first voltage domain voltage supply and a second voltage domain voltage supply when the voltage at the first signal terminal is at a high voltage;

enabling circuitry of a first circuit coupled to the first signal terminal and located in the first voltage domain to provide the first signal to the first signal terminal;

enabling circuitry of the first circuit to receive the shifted signal from the second signal terminal.

16. The method of claim 15 wherein the cutting off a current path further includes making non conductive a transistor of a first transistor and second transistor, wherein the first transistor is located in the first voltage domain and has a control terminal coupled to the first voltage domain voltage supply and the second transistor is located in the second voltage domain and has a control terminal coupled to a second voltage domain voltage supply, wherein the first transistor is made non conductive to cut off the current path when the first voltage domain voltage supply is lower than the voltage of the second voltage domain voltage supply and the second transistor is made non conductive when a voltage of the second voltage domain voltage supply is lower than a voltage of the first voltage domain voltage supply.

17. An integrated circuit with a level shifter, the level shifter comprising:

a first signal terminal configured to receive a first signal compatible with a first voltage domain of the integrated circuit;

a second signal terminal configured to output a shifted signal compatible with a second voltage domain of the integrated circuit, wherein the second voltage domain includes a power supply voltage that is higher than a power supply voltage of the first voltage domain; and

level shift circuitry located in the second voltage domain, the level shift circuitry translating the first signal received via a signal line from the first voltage domain to the shifted signal and including means for cutting off current of a current path including the signal line sourced by a second voltage domain supply when the signal line is at high voltage;

wherein the means for cutting off current includes at least one transistor coupled between the second voltage domain supply and the signal line;

wherein the at least one transistor includes a first transistor having a current terminal coupled to the signal line and a control terminal coupled to a bias circuit for maintaining a bias voltage on the control terminal, wherein the bias voltage is in a range between the power supply voltage plus a threshold of the first transistor and two transistor threshold voltages including the threshold voltage of the first transistor.

18. The integrated circuit of claim 17 , wherein the at least one transistor includes an NFET.

19. The integrated circuit of claim 17 , wherein the bias circuit includes a conductor coupled to a second voltage domain supply.

20. The integrated circuit of claim 17 , wherein the level shift circuitry is characterized as bidirectional level shift circuitry.

21. A method comprising:

providing a first signal to a first signal terminal of a level shifter, the first signal compatible with a first voltage domain, wherein in response to the providing the first signal, the level shifter provides at a second signal terminal of the level shifter a shifted signal compatible with a second voltage domain; and

providing a second signal to the signal terminal of the level shifter, the second signal compatible with the second voltage domain, wherein in response to the providing the second signal, the level shifter provides at the first signal terminal a shifted signal compatible with a first voltage domain;

cutting off current of a current path of the level shifter between a first voltage domain voltage supply and a second voltage domain voltage supply when the voltage at the first signal terminal is at a high voltage;

wherein the cutting off a current path further includes making non conductive a transistor of a first transistor and a second transistor, wherein the first transistor is located in the first voltage domain and has a control terminal coupled to the first voltage domain voltage supply and the second transistor is located in the second voltage domain and has a control terminal coupled to a second voltage domain voltage supply, wherein the first transistor is made non conductive to cut off the current path when the first voltage domain voltage supply is lower than the voltage of the second voltage domain voltage supply and the second transistor is made non conductive when a voltage of the second voltage domain voltage supply is lower than a voltage of the first voltage domain voltage supply.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2003
From: DHARNE, SHIVRAJ G.; CHUN, CHRISTOPHER K.Y.; MOUGHANNI, CLAUDE; ALI, SHAHID
To: MOTOROLA, INC.
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