System for providing a calibrated clock and methods thereof
View Patent ↗A system and methods are provided for calibrating timing in a remote device to timing in a source device. The source device dictates timing signals to be generated in the remote device. A calibration routine is processed to calibrate timing in the remote device to timing in the source device. The source device provides a reference signal that dictates a period of time to the remote device. The remote device tracks a number of local clock cycles generated for the duration of the dictated period of time. The remote device then establishes a time base for translating a number of clock cycles dictated by the source device to a number of clock cycles generated within the remote device.
1. A method comprising:
receiving a standard signal at an input of a first device, wherein the standard signal is associated with a first mode of operation;
receiving, during a second mode of operation different from the first mode of operation, at the input of the first device, a first time reference signal from a second device; and
correlating a timing event of the first time reference signal to an internal clock of the first device to determine a time base relative to a duration of time used to receive the first time reference signal.
2. The method as in claim 1 , further including receiving, at the first device, a first command from the second device and further wherein receiving the first time reference signal and correlating a timing event of the first time reference signal are performed in response to the step of receiving the first command.
3. The method as in claim 2 , wherein receipt of the first command initiates the second mode of operation.
4. The method as in claim 2 , wherein the standard signal includes a signal to enable receipt of the first command.
5. The method as in claim 2 , wherein the standard signal includes the first command.
6. The method as in claim 2 , wherein the first command is received serially.
7. The method as in claim 6 , wherein the standard signal includes a serial clock provided to establish times when bits of the first command are valid, and further wherein the first time reference signal is associated with the serial clock.
8. The method as in claim 1 , wherein the first device includes a single device of a plurality of remote devices and further wherein at least some devices of the plurality of remote devices are capable of performing the steps.
9. The method as in claim 1 , wherein the time base is determined by counting a number of cycles of the internal clock of the first device during a period of time identified using the first time reference signal.
10. The method as in claim 9 , further including modifying a count representing the number of cycles used to determine a time base.
11. The method as in claim 10 , wherein modifying the count includes using a stored register value to modify the count representing the number of cycles.
12. The method as in claim 1 , wherein the first time reference signal is part of a signal generated by the second device and is identified between two transitions of the signal generated by the second device.
13. The method as in claim 12 , wherein the first device initiates the first mode of operation in response to the second transition of the first time reference signal.
14. The method as in claim 1 , further including providing a control signal of a desired rate based on the time base.
15. The method as in claim 1 , wherein the first mode of operation is associated with a receipt of data according to a communications protocol.
16. The method as in claim 15 , wherein the communications protocol includes a protocol from the group comprising a standard communications protocol and a proprietary communications protocol.
17. The method as in claim 15 , wherein the communications protocol includes a serial communications protocol.
18. The method as in claim 1 , further including shifting a frequency associated with the time base based upon a predetermined value.
19. A system comprising:
a source device having:
a source clock to generate a source clock signal;
an output node to provide a first time reference to an input port of a first remote device;
the first remote device having:
an input node coupled to the output node of said source device to receive a standard signal in a first mode of operation and said first time reference in a second mode of operation;
a counter to identify a number of clock cycles generated by an internal clock for a duration specified through said first time reference, during said second mode of operation;
a control signal generator to determine a time base based on said number of clock cycles;
an output node to provide to a target device a control signal based on said time base;
said internal clock; and
said target device having an input node coupled to the output node of said first remote device, said input node receiving said control signal and said target device performing a function based on said control signal.
20. The system as in claim 19 , wherein said source device further includes a calibration control module, wherein said calibration control module is used to generate a calibration enable command to initiate the second mode of operation in said first remote device.
21. The system as in claim 20 , wherein said calibration enable command is further used to reset said number of clock cycles identified by said counter.
22. The system as in claim 20 , wherein said calibration enable command includes a serial command.
23. The system as in claim 22 , wherein said standard signal includes said calibration enable command.
24. The system as in claim 22 , wherein said first remote device further includes a serial communications decoder to receive said serial command, said serial communications decoder including a serial data node to receive said serial command, a serial clock node to receive a serial communications clock, and an enable port to receive a chip select signal to enable serial communications.
25. The system as in claim 24 , wherein said standard signal includes one of said serial clock or said chip select bar signal.
26. The system as in claim 19 , wherein said target device includes a stepper motor and further wherein a motion of a rotor of said stepper motor is based on said control signal.
27. The system as in claim 19 , wherein said duration of said first time reference is based on a time between two transitions of said first time reference.
28. The system as in claim 27 , wherein said two transitions include two transitions from the group comprising two rising edges and two falling edges.
29. The system as in claim 27 , wherein the two transitions include a rising edge and a falling edge.
30. The system as in claim 19 , wherein said counter includes a free running system counter.
31. The system as in claim 19 , wherein said first remote device further includes an adder used to modify the number of clock cycles identified using said counter.
32. The system as in claim 31 , wherein said first remote device further includes a register to store a value used by said adder to modify the number of clock cycles identified using said counter.
33. A system comprising:
a serial communications interface having:
a serial data node to receive serial commands, wherein said serial data node is used to receive a command to initiate a second mode of operation;
a serial clock node to receive a signal to clock in bits at the serial data node;
an enable node to receive a first enable signal to enable serial communications;
a signal node to receive a standard signal in a first mode of operation and a time reference signal in the second mode of operation, wherein a completion of the time reference signal is used to initiate the first mode of operation;
a counter to track a number of clock cycles generated by a local clock, said counter having:
a reset node to initialize a count of the number of clock cycles;
an enable node to receive a second enable signal to enable a counting of the clock cycles;
an output node to provide a count of the number of clock cycles;
a control signal generator to generate a control signal based on the count of the number of clock cycles, said control signal generator having an input node coupled to the output node of the counter to receive said count of the number of clock cycles; and
said local clock to generate said clock cycles.
34. The system as in claim 33 , wherein said enable node of the counter is coupled to the enable node of said serial communications interface.
35. The system as in claim 33 , further including an adder having an input node coupled to the output node of said counter and said adder further having an output node coupled to the input node of said control signal generator, said adder used to modify said number of clock cycles.
36. A method comprising:
receiving a first signal of a first operational type at an input of a first device, wherein the first signal is associated with a first mode of operation;
receiving at the input, during a second mode of operation, a second signal of a second operational type, wherein the first operational type is different than the second operational type; and
correlating a timing event received as part of the second signal to an internal clock of the first device to determine a time base relative to the first time reference signal.
37. The method as in claim 36 , wherein the first operational type is associated with a communications protocol.
38. The method as in claim 37 , wherein the communications protocol is associated with a transmission protocol from the group comprising a standard communications protocol and a proprietary communications protocol.
39. The method as in claim 37 , wherein the communications protocol is associated with a serial communications protocol.
40. The method as in claim 37 , wherein the first signal is associated with a signal comprising the group of a transmitted command, a data clock signal, and a chip select signal.