Semiconductor device and method for forming the same
View Patent ↗A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions ( 44, 54 ). The first portions ( 44 ) may have a first thickness, and the second portions ( 54 ) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions ( 42 ) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions ( 44 ) of the first semiconductor region and laterally between a respective pair of the second portions ( 54 ) of the first semiconductor region. A third semiconductor region ( 56 ) within the semiconductor substrate may have the first dopant type. A gate electrode ( 64 ) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region ( 56 ).
1. A semiconductor device comprising:
a semiconductor substrate having a first dopant type;
an epitaxial layer on an upper surface of the semiconductor substrate;
a first semiconductor region within the epitaxial layer and having a plurality of first portion and second portions that are laterally adjacent to the first portions, the first portions having a first thickness and the second portions having a second thickness that is greater than the first thickness, the first semiconductor region having a first concentration of a second dopant type;
a plurality of second semiconductor regions within the epitaxial layer, each second semiconductor region being positioned directly below one of the first portions of the first semiconductor region and laterally between a respective pair of the second portions of the first semiconductor region, the second semiconductor regions having the first dopant type;
a contact region within and at a surface of the epitaxial layer and adjacent to the first semiconductor region, the contact region having a second concentration of the second dopant type, the second concentration being substantially different than the first concentration;
the third semiconductor region within the epitaxial layer, the third semiconductor region having the first dopant type; and
a gate electrode over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region, wherein the first semiconductor region covers the plurality of second semiconductor regions to form a buried super-junction.
2. The semiconductor device of claim 1 , wherein each respective first portion of the first semiconductor region is positioned laterally between the respective pair of the second portions of the first semiconductor region.
3. The semiconductor device of claim 2 , wherein each respective first portion of the first semiconductor region is adjacent to the respective pair of the second portions of the first semiconductor region.
4. The semiconductor device of claim 3 , wherein each second semiconductor region is adjacent to the respective first portion of the first semiconductor region and the respective pair of the second portions of the first semiconductor region.
5. The semiconductor device of claim 1 , wherein the contact region is a drain contact region and the semiconductor device further comprising a source contact region within the epitaxial layer and adjacent to the third semiconductor region, the source contact region having a second dopant type.
6. The semiconductor device of claim 5 , wherein the drain contact region extends directly above at least some of the first portions of the semiconductor region and the respective second semiconductor regions.
7. The semiconductor device of claim 6 , further comprising a fourth semiconductor region within the semiconductor substrate and adjacent to the third semiconductor region, the fourth semiconductor region having the first dopant type.
8. The semiconductor device of claim 7 , wherein the gate electrode is laterally disposed to one side of the source contact region opposite the fourth semiconductor region.
9. The semiconductor device of claim 8 , wherein the first dopant type is P-type and the second dopant type is N-type.
10. A semiconductor device comprising:
a first semiconductor layer having a first dopant type;
a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a second dopant type;
an epitaxial layer over the second semiconductor layer;
a first semiconductor region within the epitaxial layer, the first semiconductor region having first, second, and third portions and a first concentration of the the second dopant type, wherein the first, second, and third portions are laterally adjacent to each other, and wherein the third portion has a thickness that is less than the thickness of the first and second portions;
a second semiconductor region within the epitaxial layer between the first semiconductor region and the second semiconductor layer, the second semiconductor region having the first dopant type, wherein the first and second semiconductor regions are shaped and positioned such that the first and second portions of the first semiconductor region lie on laterally opposing sides of the second semiconductor region and the third portion of the first semiconductor region is directly above the second semiconductor region;
a third semiconductor region within the epitaxial layer above the second semiconductor region, the third semiconductor region having the first dopant type;
a fourth semiconductor region within the epitaxial layer adjacent to the third semiconductor region, the fourth semiconductor region having the first dopant type;
a source contact region within the epitaxial layer adjacent to the third semiconductor region and adjacent to the fourth semiconductor region, the source contact region having a second concentration of the second dopant type;
a drain contact region within the epitaxial layer and adjacent to the first semiconductor region and above the second semiconductor region, the drain contact region having a second concentration of the second dopant type, the second concentration being substantially different than the first concentration; and
a gate electrode over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region, the gate electrode being laterally disposed to one side of the source contact region opposite the fourth semiconductor region, wherein the second semiconductor region is disposed laterally between the first and second portions of the first semiconductor region to form a buried super-junction.
11. The semiconductor device of claim 10 , wherein the first, second, and third portions of the first semiconductor region are adjacent to the second semiconductor region and the drain contact region.
12. The semiconductor device of claim 11 , wherein the drain contact region extends directly over the first, second, and third portions of the first semiconductor region.
13. The semiconductor device of claim 12 , wherein the third portion of the first semiconductor region is adjacent to the first and second portions of the first semiconductor region.
14. The semiconductor device of claim 13 , wherein the first dopant type is P-type and the second dopant type is N-type.
15. A method for constructing a semiconductor device comprising:
forming a first semiconductor region in an epitaxial layer on a semiconductor substrate, the first semiconductor region having a plurality of first portions and second portions that are laterally adjacent to the first portions, the first portions having a first thickness and the second portions having a second thickness that is greater than the first thickness, the semiconductor substrate having a first dopant type and the first semiconductor region having first concentration of a second dopant type;
forming a plurality of second semiconductor regions within the epitaxial layer, each second semiconductor region being positioned directly below one of the first portions of the first semiconductor region and laterally between a respective pair of the second portions of the first semiconductor region;
forming a contact region within and at a surface of the epitaxial layer and adjacent to the first semiconductor region, the contact region having a second concentration of the second dopant type, the second concentration being substantially different than the first concentration;
forming a third semiconductor region within the epitaxial layer the third semiconductor region having a first dopant type; and
forming a gate electrode over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region, wherein the first semiconductor region covers the plurality of the second semiconductor regions to form a buried super-junction.
16. The method of claim 15 , wherein each respective first portion of the first semiconductor region is positioned laterally between and is adjacent to the respective pair of the second portions of the first semiconductor region.
17. The method of claim 16 , wherein each second semiconductor region is adjacent to the respective first portion of the first semiconductor region and the respective pair of the second portions of the first semiconductor region.
18. The method of claim 15 wherein the contact region is a drain contact region over at least some of the first and second portions of the first semiconductor region and the respective second semiconductor regions and further comprising forming a source contact region within the semiconductor substrate and adjacent to the third semiconductor region, the source contact region having the second dopant type.
19. The method of claim 18 , wherein the first dopant type is P-type and the second dopant type is N-type.