Device and method for arbitrating between direct memory access task requests
View Patent ↗A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.
1. A method for arbitrating between direct memory access (DMA) task requests, the method comprises:
defining a plurality of timing deadline ranges, each timing deadline range comprising a plurality of timing deadlines;
receiving multiple DMA task requests, wherein each DMA task request includes a current counter field for storing a current value of a timing counter, and a threshold field for storing a threshold value, wherein the threshold value reflects a value of the timing counter when the associated DMA task is due, and wherein a difference between the current value of the timing counter and the threshold value represents a timing deadline for the associated DMA task;
sorting the multiple DMA task requests into the plurality of timing deadline ranges based upon the timing deadlines associated with the respective DMA tasks;
selecting a first DMA task request out of the multiple DMA task requests, wherein the selecting includes selecting one of a plurality of DMA task requests associated with a particular timing deadline range;
determining that a first timing deadline of the first DMA task has passed, wherein the first timing deadline occurs prior to a time when the current value of the timing counter for the first DMA task equals the threshold value for the first DMA task; and
increasing a priority of the first DMA task in response to determining that the first timing deadline has passed;
wherein at least one DMA task is a cyclic time based DMA task that has a repetition rate that is limited by a DMA task execution period.
2. The method according to claim 1 wherein each DMA task request of the plurality of DMA task requests associated with the particular timing deadline range has substantially a same timing deadline.
3. The method according to claim 1 , wherein at least one DMA task request of the plurality of DMA task requests is a cyclic time based DMA task, wherein only a single cyclic time based DMA task is executed during a single DMA task execution period.
4. The method according to claim 1 , wherein each DMA task is associated with an I/O port and wherein the selecting comprises arbitrating between DMA task requests that are associated to the same I/O port.
5. The method according to claim 1 , wherein at least one DMA task request involves retrieving information from a multidimensional buffer; wherein each dimension of the multidimensional buffer is associated with a different DMA sub task of the DMA task.
6. The method according to claim 1 , further comprising generating an interrupt at an end of a DMA task execution sub-interval, in response to a possible timing deadline violation, wherein the possible timing deadline violation is detected, before a timing violation occurred, if a DMA task that was expected to be completed during a DMA task execution interval was not completed during the DMA task execution sub-interval.
7. A device that comprises:
an interface that is adapted to:
define a plurality of timing deadline ranges, each timing deadline range comprising a plurality of timing deadlines; and
receive multiple direct memory access (DMA) task requests, wherein each DMA task includes a current counter field for storing a current value of a timing counter, and a threshold for storing a threshold value, wherein the threshold value reflects a value of the timing counter when the associated DMA task is due, and wherein a difference between the current value of the timing counter and the threshold value represents a timing deadline for the associated DMA task;
an arbiter that is adapted to:
sort the multiple DMA task requests into the plurality of timing deadline ranges in response to the timing deadlines associated with the respective DMA tasks;
select a first DMA task request out of the multiple DMA task requests, wherein in selecting, the arbiter is further adapted to select one of a plurality of DMA task requests associated with a particular timing deadline range of the plurality of timing deadline ranges;
determine that a first timing deadline of the first DMA task has passed, wherein the first timing deadline occurs prior to a time when the current value of the timing counter for the first DMA task equals the threshold value for the first DMA task; and
increase a priority of the first DMA task in response to determining that the first timing deadline has passed.
8. The device according to claim 7 wherein each DMA task request of the plurality of DMA task requests associated with the particular timing deadline range has substantially a same timing deadline.
9. The device according to claim 7 , wherein at least one DMA task request of the plurality of DMA task requests is a cyclic time based DMA task, wherein only a single cyclic time based DMA task is executed during a single DMA task execution period.
10. The device according to claim 7 , wherein at least one DMA task request involves retrieving information from a multidimensional buffer; wherein each dimension of the multidimensional buffer is associated with a different DMA sub task of the DMA task.
11. The device according to claim 7 , further adapted to generate an interrupt at an end of a DMA task execution sub-interval, in response to a possible timing deadline violation, wherein the possible timing deadline violation is detected, before a timing violation occurred, if a DMA task that was expected to be completed during a DMA task execution interval was not completed during the DMA task execution sub-interval.
12. The device according to claim 7 , comprising multiple ports and wherein the arbiter is adapted to arbitrate between DMA tasks associated with a single port.
13. The method according to claim 1 , further comprising allowing, in response to a possible timing deadline violation, more than a single DMA cyclic time based DMA task to be executed during a next DMA task execution period.
14. The device according to claim 7 , further adapted to allow, in response to a possible timing deadline violation, more than a single DMA cyclic time based DMA task to be executed during a next DMA task execution period.
15. The method according to claim 1 wherein the selected DMA task request has other than a shortest timing deadline of the plurality of DMA task requests.
16. The device according to claim 7 wherein the selected DMA task request has other than a shortest timing deadline of the plurality of DMA task requests.
17. The method according to claim 1 , wherein:
each DMA task further includes a base counter field that includes a base counter value that is loaded to the current counter field when the associated DMA task is initialized; and
each DMA task has an associated DMA task execution period that is defined as a first difference between an associated base counter value and an associated timing deadline.
18. The method according to claim 1 , further comprising:
forcing an execution of the first DMA task in further response to determining that the first timing deadline has passed.
19. The device according to claim 7 , wherein:
each DMA task further includes a base counter field that includes a base counter value that is loaded to the current counter field when the associated DMA task is initialized and a third timing field that includes a current time value; and
each DMA task has an associated DMA task execution period that is defined as a first difference between an associated base counter value and an associated timing deadline.