Distributed resource access protection
A method includes determining, at a first requesting component of an integrated circuit device, a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting component. The method further includes transmitting the first key value from the first requesting component to a resource component of the integrated circuit device. The method also includes determining, at the resource component, an authorization of the first access request based on the first key value and a second set of one or more bits of the first address.
1. A method comprising:
determining, at a first requesting component of an integrated circuit device, a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting component, wherein determining the first key value comprises accessing a first key table associated with the first requesting component, the first key table comprising a plurality of key value entries indexed based on the first set of one or more bits;
transmitting the first key value from the first requesting component to a resource component of the integrated circuit device;
determining, at the resource component, an authorization of the first access request based on the first key value and a second set of one or more bits of the first address;
determining, at a second requesting component of the integrated circuit device, a second key value based on a third set of one or more bits of a second address associated with a second access request of the second requesting component;
transmitting the second key value from the second requesting component to the resource component of the integrated circuit device; and
determining, at the resource component, an authorization of the second access request based on the second key value and a fourth set of one or more bits of the second address.
2. The method of claim 1 , wherein at least one bit of the first set of one or more bits is different from at least one bit of the second set of one or more bits.
3. The method of claim 2 , wherein the first set of one or more bits and the second set of one or more bits comprise mutually exclusive sets of bits.
4. The method of claim 1 , wherein determining the second key value comprises accessing a second key table associated with the second requesting component, the second key table comprising a plurality of key value entries indexed based on the second set of one or more bits.
5. The method of claim 1 , further comprising transmitting the first access request from the first requesting component to the resource component.
6. The method of claim 1 , further comprising:
determining, at the first requesting component, the first address; and
transmitting the first address from the first requesting component to the resource component;
wherein determining the first address and determining the first key value occur during a first operation cycle of the integrated circuit device; and
wherein transmitting the first address and determining the authorization of the first access request occur during a second operation cycle of the integrated circuit device, wherein the second operation cycle is subsequent to the first operation cycle.
7. A method comprising:
during a first operational cycle of an integrated circuit device:
determining, at a first requesting component of the integrated circuit device, an address associated with an access request of the first requesting component; and
accessing an entry of a key table to determine a first key value, wherein the entry of the key table is indexed based on a first set of one or more bits of the address;
during a second operational cycle of the integrated circuit device subsequent to the first operational cycle:
transmitting the address and the first key value from the first requesting component to a resource component; and
determining, at the resource component, an authorization of the access request based on the first key value and a second set of one or more bits of the address;
during a third operational cycle of the integrated circuit device subsequent to the second operational cycle:
determining, at a second requesting component, a second key value based on a third set of one or more bits of a second address associated with a second access request of the second requesting component; and
during a fourth operational cycle of the integrated circuit device subsequent to the third operational cycle:
transmitting the second key value from the second requesting component to the resource component; and
determining, at the resource component, an authorization of the second access request based on the second key value and a fourth set of one or more bits of the second address.
8. The method of claim 7 , further comprising:
performing the access request at the resource component during a third operation cycle of the integrated circuit device subsequent to the second operation cycle in response to determining the access request is authorized.
9. The method of claim 7 , wherein the resource component comprises a plurality of memory regions selectively accessible by the requesting component based on a memory access scheme.
10. The method of claim 7 , wherein the key table is configured based on the memory access scheme.
11. An integrated circuit device comprising:
a first requesting hardware component of the integrated circuit device comprising logic to determine a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting hardware component and logic to provide the first key value for transmission via a bus;
a resource component comprising logic to determine an authorization of the first access request based on the first key value and a second set of one or more bits of the first address;
a first key table associated with the first requesting hardware component and comprising a plurality of key value entries, wherein the logic of the first requesting hardware component determines the first key value by accessing the first key table based on the first set of one or more bits;
a second requesting component comprising logic to determine a second key value based on a third set of one or more bits of a second address associated with a second access request of the second requesting component and logic to provide the second key value for transmission via the bus; and
wherein the resource component comprises logic to determine an authorization of the second access request based on the second key value and a fourth set of one or more bits of the second address.
12. The integrated circuit device of claim 11 , wherein at least one bit of the first set of one or more bits is different from at least one bit of the second set of one or more bits.
13. The integrated circuit device of claim 12 , wherein first set of one or more bits and the second set of one or more bits comprise mutually exclusive sets of bits.
14. The integrated circuit of claim 11 , further comprising:
a second key table associated with the second requesting component and comprising a plurality of key value entries, wherein the logic of the second requesting component determines the second key value by accessing the second key table based on the third set of one or more bits.
15. The integrated circuit of claim 11 , wherein first requesting component further comprises logic to provide the first access request for transmission to the resource component via the bus.
16. The integrated circuit of claim 11 , wherein:
the first requesting component further comprises logic to determine the first address and provide the first address for transmission via the bus;
wherein the logic of the first requesting component determines the first address and determines the first key value during a first operation cycle of the integrated circuit device; and
wherein the logic of the first requesting component provides the first address for transmission and the first key value and the logic of the resource component determines the authorization of the first access request during a second operation cycle of the integrated circuit device, wherein the second operation cycle is subsequent to the first operation cycle.