Sequence-independent power-on reset for multi-voltage circuits
View Patent ↗A power-on reset (“POR”) methodology and circuit for an electronic circuit using multiple supply voltage domains asserts a reset signal upon ramp up of the first supply voltage signal, maintains the reset signal until all of the supply voltage signals have ramped up, and de-asserts the reset signal after all of the supply voltage signals have ramped up. Practical embodiments of the POR circuit include a control circuit that reduces static and/or dynamic current leakage associated with the operation of the POR circuit.
1. A power-on reset (“POR”) circuit for a multi-voltage circuit, said POR circuit comprising:
a POR node for a POR output signal;
a pull-up circuit comprising a pull-up output node coupled to said POR node, and having pull-up input nodes for receiving a plurality of supply voltage signals, wherein said pull-up circuit comprises a plurality of PMOS transistors, each having a drain coupled to said POR node, and each having a source coupled to one of said pull-up input nodes; and
a pull-down circuit comprising a pull-down output node coupled to said POR node, and having pull-down input nodes for receiving said plurality of supply voltage signals, wherein said pull down circuit comprises a plurality of NMOS transistors coupled in series between said POR node and a low reference potential, each of said NMOS transistors having a gate coupled to one of said pull-down input nodes;
wherein said pull-up circuit and said pull-down circuit generate a high POR output signal at said POR node in response to ramp-up of a first supply voltage signal, wherein ramp-up of said first supply voltage signal occurs first in time, and wherein said pull-up circuit and said pull-down circuit generate a low POR output signal at said POR node in response to ramp-up of a last supply voltage signal, wherein ramp-up of said last supply voltage signal occurs last in time.
2. The POR circuit of claim 1 , wherein said plurality of supply voltage signals are sequence-independent signals.
3. The POR circuit of claim 1 , further comprising a POR signal generator having an input node coupled to said POR node, said POR signal generator generating at least one module reset signal for the multi-voltage circuit.
4. The POR circuit of claim 3 , wherein said POR signal generator has N output nodes for N module reset signals corresponding to N supply voltages.
5. The POR circuit of claim 1 , further comprising a control circuit coupled to said pull-up circuit, said control circuit influencing operation of said pull-up circuit to reduce steady state current consumption associated with generation of said high POR output signal and said low POR output signal.
6. The POR circuit of claim 1 , further comprising a control circuit coupled to said pull-up circuit, said control circuit influencing operation of said pull-up circuit to reduce dynamic current consumption associated with generation of said high POR output signal and said low POR output signal.
7. The POR circuit of claim 1 , further comprising a control circuit coupled to said pull-up circuit, said control circuit influencing operation of said pull-up circuit to reduce steady state and dynamic current consumption associated with generation of said high POR output signal and said low POR output signal.
8. A power-on reset (“POR”) circuit for a multi-voltage circuit having N supply voltages, said POR circuit comprising:
a POR node for a POR output signal;
N PMOS transistors, each having a drain coupled to said POR node, and each having a source for receiving a different one of N supply voltage signals;
N NMOS transistors coupled in series between said POR node and a low reference potential, each of said NMOS transistors having a gate for receiving a different one of said N supply voltage signals;
said PMOS transistors and said NMOS transistors generating a high POR output signal at said POR node if at least one, but not all, of said supply voltage signals has ramped up, and generating a low POR output signal if all of said supply voltage signals have ramped up; and
a control circuit coupled to said PMOS transistors, said control circuit influencing operation of said PMOS transistors to reduce steady state and dynamic current consumption associated with generation of said high POR output signal and said low POR output signal.
9. The POR circuit of claim 8 , wherein said supply voltage signals are sequence-independent signals.