Device and method for handling metastable signals
View Patent ↗A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points.
1. A device having metastable signal handling capabilities, the device comprises:
a pull down circuit and a pull up circuit;
a first latch including an inverter with a switching point between a high switching point and a low switching point;
a second latch; and
a multiple switching point circuit, coupled between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit comprises at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to an output signal of the first latch such as to define at least the low switching point that is lower than the high switching point of the multiple-switching point circuit;
wherein:
a first portion of the pull down circuit and a first portion of the pull up circuit are activated when the feedback signal has a first value and wherein a second portion of the pull down circuit and a second portion of the pull up circuit are activated when the feedback signal has a second value that differs from the first value;
wherein the first portion of the pull down circuit differs from the second portion of the pull down circuit; and
wherein the first portion of the pull up circuit differs from the second portion of the pull up circuit.
2. The device according to claim 1 wherein an output node of the second latch provides the feedback signal.
3. The device according to claim 2 wherein the multiple switching point circuit further comprises a first inverter that is activated regardless of the feedback signal.
4. The device according to claim 2 wherein the first latch receives a first clock signal and the second latch receives a second clock signal and wherein there is a time gap between a transition of the first clock signal and a transition of the second clock signal.
5. The device according to claim 1 wherein the multiple switching point circuit further comprises a first inverter that is activated regardless of the feedback signal.
6. The device according to claim 1 wherein the first latch receives a first clock signal and the second latch receives a second clock signal and wherein there is a time gap between a transition of the first clock signal and a transition of the second clock signal.
7. The device according to claim 1 wherein the first portion of the pull up circuit is stronger than the first portion of the pull down circuit and wherein the second portion of the pull up circuit is weaker than the second portion of the pull down circuit.
8. The device according to claim 1 wherein a feedback inverter of the first latch switches before the multiple switching point circuit.
9. The device according to any claim 1 wherein the multiple switching point circuit comprises an input inverter coupled to a sequence of transistors that comprises at least two transistors that are selectively activated in response to a level of the feedback signal.
10. The device according to claim 9 wherein the sequence of transistors further comprises at least two transistors that are selectively activated in response to a level of a signal provided from an output node of a first inverter.
11. Information processing apparatus comprising a device according to claim 1 .
12. A device having metastable signal handling capabilities, the device comprises:
a first latch including an inverter with a switching point between a high switching point and a low switching point;
a second latch; and
a multiple switching point circuit, coupled between an output node of the first latch and an input node of the second latch, the multiple switching point circuit comprising:
at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to an output signal of the first latch such as to define at least the low switching point that is lower than the high switching point of the multiple-switching point circuit; and
an input inverter coupled to a sequence of transistors that comprises at least two transistors that are selectively activated in response to a level of the feedback signal, wherein the sequence of transistors further comprises at least two transistors that are selectively activated in response to a level of a signal provided from an output node of a first inverter.
13. A device having metastable signal handling capabilities, the device comprises:
a first latch including an inverter with a switching point between a high switching point and a low switching point,;
a second latch; and
a multiple switching point circuit, coupled between an output node of the first latch and an input node of the second latch, the multiple switching point circuit comprising:
at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to an output signal of the first latch such as to define at least the low switching point that is lower than the high switching point of the multiple-switching point circuit;
a pull down circuit; and
a pull up circuit;
wherein:
the first latch receives a first clock signal and the second latch receives a second clock signal and wherein there is a time gap between a transition of the first clock signal and a transition of the second clock signal;
a first portion of the pull down circuit and a first portion of the pull up circuit are activated when the feedback signal has a first value and wherein a second portion of the pull down circuit and a second portion of the pull up circuit are activated when the feedback signal has a second value that differs from the first value;
the first portion of the pull down circuit differs from the second portion of the pull down circuit; and
wherein the first portion of the pull up circuit differs from the second portion of the pull up circuit.