Method of forming a semiconductor structure
View Patent ↗A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium.
1. A method of forming a semiconductor structure, the method comprising the steps of:
disposing a first layer of semiconductor material;
disposing a second layer of semiconductor material adjacent the first layer of semiconductor material;
disposing a third layer of semiconductor material adjacent the second layer of semiconductor material;
disposing a gate insulator layer over the third layer;
disposing a gate electrode layer over the gate insulator layer;
forming a pair of trenches through at least the third layer to expose the second layer of semiconductor material for access by an etchant thereto, the pair of trenches disposed on opposite sides of the gate insulator layer and the gate electrode layer;
exposing the second layer of semiconductor material to a thermal gaseous chemical etchant, the thermal gaseous etchant laterally and isotropically etching the second layer of semiconductor material so as to form a cavity between the first and third layers of semiconductor material, wherein the second layer of semiconductor material is formed from a different material to the first and third layers of semiconductor material; and
depositing a sidewall spacer material to form a sidewall on the gate insulator and the gate electrode, the sidewall spacer material depositing into the cavity.
2. A method as claimed in claim 1 , wherein the thermal gaseous etchant is selective in favour of etching the second layer of semiconductor material.
3. A method as claimed in claim 1 , wherein the thermal gaseous etchant is at a temperature of between about 700 degree C. and 800 degree C.
4. A method as claimed in claim 1 , wherein the thermal gaseous etchant is at a temperature of between about 600 degree C. and 900 degree C.
5. A method as claimed in claim 1 , wherein the thermal gaseous etchant is exposed to the second layer of semiconductor material under a predetermined pressure.
6. A method as claimed in claim 5 , wherein the predetermined pressure is between about 10 mTorr and about 500 mTorr.
7. A method as claimed in claim 6 , wherein the predetermined pressure is between about 50 mTorr and about 100 mTorr.
8. A method as claimed in claim 1 , wherein the first layer of semiconductor material is formed from a different material to the third layer of semiconductor material.
9. A method as claimed in claim 1 , wherein the first layer of semiconductor material is a silicon layer.
10. A method as claimed in claim 1 , wherein the third layer of semiconductor material is silicon.
11. A method as claimed in claim 1 , wherein the second layer of semiconductor material is a sacrificial layer.
12. A method as claimed in claim 1 , wherein the second layer of semiconductor material is a Silicon-Germanium layer.
13. A method as claimed in claim 1 , wherein the thermal gaseous chemical etchant is gaseous Hydrochloric Acid.
14. A method as claimed in claim 1 , wherein the semiconductor structure is a transistor.
15. A method as claimed in claim 14 , wherein the transistor is a Field Effect Transistor.
16. A method as claimed in claim 14 , wherein the transistor is a Complementary Metal Oxide Semiconductor transistor.
17. A method as claimed in claim 1 , wherein the first layer of semiconductor material is a substrate.
18. A method as claimed in claim 1 , depositing the sidewall space material fills the cavity with a dielectric material.
19. A method as claimed in claim 1 , wherein thermal gaseous chemical etchant is mixed with a dilutant gas.
20. A method as claimed in claim 19 , the dilutant gas is an inert gas.
21. A method of forming a semiconductor structure, the method comprising:
depositing a second layer of semiconductor material adjacent a major surface of a first layer of semiconductor material;
growing a third layer of semiconductor material adjacent a major surface of the second layer of semiconductor material opposite the major surface of the first layer of semiconductor material;
depositing a gate insulator layer over the third layer;
depositing a gate electrode layer over the gate insulator layer;
forming a gate stack from the gate insulator layer and the gate electrode layer, the gate stack having a gate stack profile;
forming a pair of trenches through at least the third layer to expose the second layer of semiconductor material for access by an etchant thereto, the pair of trenches disposed on opposite sides of the gate stack at edges of the gate stack profile;
exposing the second layer of semiconductor material to a thermal gaseous chemical etchant, the thermal gaseous etchant laterally and isotropically etching the second layer of semiconductor material so as to form a cavity between the first and third layers of semiconductor material; and
depositing a sidewall spacer material to form a sidewall on the gate stack, the sidewall spacer material depositing into the cavity.