Granted Patent B2

US 7,528,015 · App. 11/169,962 · Granted May 5, 2009

Abstract

Claims (14)

1. A method for forming an antifuse element, comprising:

determining a target breakdown voltage;

providing a substrate;

forming an active area within the substrate;

forming a first gate oxide layer on the active area;

applying a dual gate oxide (DGO) mask over a portion of the first gate oxide layer, thereby defining a DGO masked region;

etching away a portion of the gate oxide outside the DGO masked region and a portion of the substrate outside the DGO masked region such that the substrate has a first gradual step structure along an edge of the DGO masked region;

removing the DGO mask;

forming a second oxide layer over the first gradual step structure of the substrate and the first oxide layer to produce a combined oxide layer having a second gradual step structure over the first gradual step structure, wherein the first gradual step structure has a first slope, the second gradual step structure has a second slope, and the second slope has the same slope direction but a greater slope magnitude than the first slope;

forming a gate electrode over the combined oxide layer such that the combined oxide layer, gate electrode, and active area of the substrate form a rupture region having an actual breakdown voltage substantially equal to the target breakdown voltage.

2. The method of claim 1 , wherein the active area comprises a heavily doped diffusion contact.

3. The method of claim 1 , wherein the combined oxide layer has a submicron minimum thickness, and a maximum thickness that is greater than the minimum thickness.

4. The method of claim 1 , wherein the gate electrode is formed from polysilicon.

5. The method of claim 1 , wherein the DGO mask is applied in connection with formation of a dual gate metal oxide field effect transistor (MOSFET).

Assignments (23)