Integrated circuit having a non-volatile memory with discharge rate control and method therefor
View Patent ↗An integrated circuit includes a memory ( 10 ). The memory ( 10 ) includes an array ( 12 ) of non-volatile memory cells. Each memory cell ( 14 ) of the array ( 12 ) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array ( 12 ), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit ( 11 ) controls the discharging of terminals of the memory cell. The discharge rate control circuit ( 11 ) includes, for example, a plurality of parallel-connected transistors ( 112 ) coupled between the array ( 12 ) of non-volatile memory cells and a power supply terminal.
1. An integrated circuit comprising:
an array of non-volatile memory cells, each memory cell of the array having a charge storage region and a plurality of terminals;
a discharge rate control circuit for controlling a discharge rate of one or more of the plurality of terminals of an erased memory cell, the discharge rate control circuit comprising a plurality of parallel-connected transistors coupled between the one or more of the plurality of terminals and a power supply terminal; and
a high voltage protection circuit, coupled to the discharge rate control circuit, for protecting the plurality of parallel-connected transistors from damage due to exposure to relatively high erase voltages.
2. The integrated circuit of claim 1 , wherein the array of non-volatile memory cells comprises an array of flash memory cells.
3. The integrated circuit of claim 1 , wherein one or more transistors of the plurality of parallel-connected transistors are conductive for a first predetermined time to provide a first discharge rate, and one or more transistors of the plurality of parallel-connected transistors are conductive for a second predetermined time to provide a second discharge rate higher than the first discharge rate.
4. The integrated circuit of claim 1 , wherein the plurality of terminals comprises a control gate, a drain, and a source.
5. The integrated circuit of claim 1 , wherein the drain of each of the memory cells of the array is coupled to a corresponding hit line and all of the sources of the array are coupled together.
6. The integrated circuit of claim 1 , wherein each transistor of the plurality of parallel-connected transistors has a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a control signal, and a second current electrode.
7. The integrated circuit of claim 6 , further comprising:
a first transistor having a first current electrode coupled to the second current electrode of each transistor of the plurality of parallel-connected transistors, a control electrode for receiving a first bias voltage, and a second current electrode;
a second transistor having a first current electrode and a control electrode both coupled to the second current electrode of the first transistor, and a second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving a second bias voltage, and a second current electrode; and
a fourth transistor having a first current electrode and a control electrode both coupled to the second current electrode of the third transistor, and a second current electrode coupled to a second power supply voltage terminal.
8. The integrated circuit of claim 7 , wherein the first, second, third, and fourth transistors have a relatively thicker gate oxide than a gate oxide of the plurality of parallel-connected transistors.
9. The integrated circuit of claim 1 , wherein the charge storage region is a floating gate of a flash memory cell.
10. An integrated circuit comprising:
an array of non-volatile memory cells, each memory cell of the array having a control gate, a source, a drain, a first well terminal, and a second well terminal; and
a discharge rate control circuit for controlling discharging of erase voltages from the control gate, the source, the drain, the first well terminal and the second well terminal of an erased memory cell after an erase operation of the array of non-volatile memory cells, the discharge rate control circuit comprising a plurality of parallel-connected transistors coupled between the array of non-volatile memory cells and a power supply terminal.
11. The integrated circuit of claim 10 , wherein the array of non-volatile memory cells comprises an array of flash memory cells.
12. The integrated circuit of claim 10 , wherein one or more transistors of the plurality of parallel-connected transistors are conductive for a first predetermined time to provide a first discharge rate, and one or more transistors of the plurality of parallel-connected transistors are conductive for a second predetermined time to provide a second discharge rate higher than the first discharge rate.
13. The integrated circuit of claim 10 , wherein the drain of each of the memory cells of the array is coupled to a corresponding bit line and all of the sources of the array are coupled together.
14. The integrated circuit of claim 10 , further comprising a high voltage protection circuit for protecting the plurality of parallel-connected transistors from damage due to exposure to relatively high erase voltages.
15. The integrated circuit of claim 10 , wherein each transistor of the plurality of parallel-connected transistors has a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a control signal, and a second current electrode.
16. The integrated circuit of claim 15 , further comprising:
a first transistor having a first current electrode coupled to the second current electrode of each transistor of the plurality of parallel-connected transistors, a control electrode for receiving a first bias voltage, and a second current electrode;
a second transistor having a first current electrode and a control electrode both coupled to the second current electrode of the first transistor, and a second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving a second bias voltage, and a second current electrode; and
a fourth transistor having a first current electrode and a control electrode both coupled to the second current electrode of the third transistor, and a second current electrode coupled to a second power supply voltage terminal.
17. The integrated circuit of claim 16 , wherein the first, second, third, and fourth transistors have a relatively thicker gate oxide than a gate oxide of the plurality of parallel-connected transistors.
18. A method for controlling a discharge rate of an erase voltage applied to a non-volatile memory cell, the non-volatile memory cell having a plurality of terminals, the method comprising:
providing a plurality of parallel-connected transistors coupled between one or more terminal(s) of the plurality of terminals;
erasing the non-volatile memory cell by applying the erase voltage to the non-volatile memory cell;
discharging the erase voltage through one or more transistors of the plurality of parallel-connected transistors at a first discharge rate for a first time period; and
discharging the erase voltage through one or more transistors of the plurality of parallel-connected transistors at a second discharge rate for a second time period, wherein the second discharge rate is higher than the first discharge rate and the second time period follows the first time period.
19. The method of claim 18 , wherein the plurality of terminals comprises a control gate, a floating gate, a source, a drain, and a well region, the well region being in a semiconductor substrate.