Method and apparatus for protecting an integrated circuit from erroneous operation
View Patent ↗A data processing system ( 10 ) has an embedded non-volatile memory ( 22 ) that is programmed and erased by use of a high voltage provided by a charge pump ( 78 ). In order to prevent the non-volatile memory ( 22 ) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump ( 78 ) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit ( 110 ) in response to a program or erase operation being initiated. A control register ( 76 ) will provide a high voltage enable signal to the charge pump ( 78 ) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit ( 110 ) may be enabled by another condition to protect the data processing system ( 10 ) from an authorized access.
1. An integrated circuit comprising:
a processing unit for executing instructions;
a circuit, coupled to the processing unit, for implementing a first predetermined operation in response to receiving a control signal from the processing unit; and
a low voltage detection circuit for determining if a power supply voltage provided to the integrated circuit is below a predetermined voltage level, wherein in response to the first predetermined operation being performed in the circuit, a voltage detection enable signal is provided to enable operation of the low voltage detection circuit, and if the power supply voltage is below the predetermined voltage level, the low voltage detection circuit for causing a second predetermined operation to be initiated in the integrated circuit.
2. The integrated circuit of claim 1 , wherein the integrated circuit is a microcontroller having the processing unit and one or more peripherals.
3. The integrated circuit of claim 1 , wherein the circuit is a non-volatile memory.
4. The integrated circuit of claim 3 , wherein the first predetermined operation is one of a program operation or an erase operation.
5. The integrated circuit of claim 3 , wherein the second predetermined operation causes the first predetermined operation to be stopped.
6. The integrated circuit of claim 5 , further comprising a charge pump coupled to the non-volatile memory, wherein the second predetermined operation causes the charge pump to be disabled.
7. The integrated circuit of claim 1 , wherein the second predetermined operation causes the integrated circuit to be reset to an initial condition.
8. The integrated circuit of claim 1 , wherein the control signal is provided by a control register coupled to the circuit.
9. A circuit comprising:
a first logic circuit for providing a first detection enable signal responsive to program and erase signals;
a voltage detection circuit coupled to a power supply terminal for asserting a voltage valid signal in response to the detection enable signal if a voltage at the power supply terminal is above a predetermined level;
a second logic circuit for generating a charge pump enable signal in response to the voltage valid signal; and
a charge pump that is discharged in response to the charge pump enable signal not being asserted.
10. The circuit of claim 9 , wherein the voltage detection circuit is a portion of a low voltage inhibit circuit.
11. The circuit of claim 10 , wherein the low voltage inhibit circuit comprises:
a control register bit having an output for providing a second detection enable signal;
a third logic circuit for receiving the first detection enable signal and the second detection enable signal and an output coupled to the voltage detection circuit;
the voltage detection circuit coupled to the third logic circuit; and
a fourth logic circuit coupled to the voltage detection circuit for providing a low voltage interrupt signal.
12. The circuit of claim 9 , wherein the first logic circuit and the second logic circuit include a transistor that has a relatively lower threshold voltage than other transistors of the circuit for providing more reliable operation when the voltage at the power supply terminal is below the predetermined level.
13. A method of disabling a charge pump, comprising:
providing a first detection enable signal responsive to one of a program signal and an erase signal;
providing a voltage valid signal in response to the first detection enable signal if a voltage at the power supply terminal is above a predetermined level; and
disabling the charge pump in response to the voltage valid signal not being asserted.
14. The method of claim 13 , wherein the charge pump is further characterized as generating a high voltage for programming and erasing a non-volatile memory when the charge pump is enabled.
15. The method of claim 14 , wherein the disabling is further characterized as disabling the charge pump in response to a high voltage enable signal when the high voltage enable signal is not asserted.
16. The method of claim 15 , wherein the high voltage enable signal is not asserted in response to one or more of:
a block protection signal being asserted;
an occurrence of a program or erase control sequence error, a reset signal is asserted; and
the voltage valid signal is not being asserted.
17. The method of claim 16 , further comprising:
providing a second detection enable signal from a register;
wherein the providing the voltage valid signal further comprises:
generating a third detection enable signal responsive to one or both of the first and second detection enable signals being asserted.
18. A method of preventing programming or erasing of a non-volatile memory that is coupled to a power supply terminal and that is programmed and erased using a high voltage, comprising:
providing a first detection enable signal responsive to one of a program signal and an erase signal;
providing a voltage valid signal in response to the first detection enable signal if a voltage at the power supply terminal is above a predetermined level; and
preventing the high voltage from being applied to the non-volatile memory in response to the voltage valid signal not being asserted.
19. The method of claim 18 , wherein the non-volatile memory is part of an integrated circuit and the high voltage is provided external from the integrated circuit, and wherein the preventing the high voltage comprises blocking the high voltage from reaching the non-volatile memory.
20. The method of claim 18 , wherein the preventing the high voltage comprises disabling a charge pump in response to the voltage valid signal not being asserted.
21. The method of claim 18 , wherein the high voltage enable signal is not asserted in response to one or more of (1) a block protection signal being asserted, (2) an occurrence of a program or erase control sequence error, (3) a reset signal is asserted, and (4) the voltage valid signal is not being asserted.
22. The method of claim 18 , further comprising:
providing a second detection enable signal from a register;
wherein the providing the voltage valid signal further comprises:
generating a third detection enable signal responsive to one or both of the first and second detection enable signals being asserted.
23. The method of claim 22 , further comprising generating a voltage low signal in response to the voltage at the power supply terminal being below the predetermined voltage and generating a low voltage interrupt signal in response to the voltage low signal being generated.
24. A processing unit having an embedded non-volatile memory that is programmed and erased using a high voltage, comprising
a processing unit, coupled to a power supply terminal, for generating address control signals;
a control circuit for generating a first detection enable signal in response to the address control signals; and
a voltage detection circuit for generating a voltage valid signal in response to the first detection enable signal if a voltage at the power supply terminal is above a predetermined voltage; and
prevention means for preventing the high voltage from reaching the non-volatile memory in response to the voltage valid signal not being asserted.
25. The processing unit of claim 24 , wherein the high voltage is generated external to the processing unit and the prevention means blocks the high voltage from reaching the non-volatile memory.
26. The processing unit of claim 24 , wherein the prevention means comprises a charge pump that is disabled in response to the voltage valid signal not being asserted.
27. The processing unit of claim 26 , wherein the control circuit comprises:
a control register for generating a program signal and a erase signal in response to the address control signals; and
a first logic circuit for generating the first detection enable signal in response to the program and erase signals.
28. The processing unit of claim 27 , further comprising a register for providing a second detection enable signal, wherein the first logic circuit comprises:
a second logic circuit having a first input for receiving the program signal, a second input for receiving the erase signal, and an output; and
a third logic circuit having a first input for receiving the second detection enable signal, a second input coupled to the output of the second logic circuit, and an output for providing the first detection enable signal.
29. The processing unit of claim 28 , wherein the voltage detection circuit is further characterized as generating a voltage low signal in response to the voltage at the power supply terminal being below the predetermined voltage, further comprising logic means for generating a low voltage interrupt signal in response to the voltage low signal.
30. A circuit for preventing a change in logic states of memory cells of a non-volatile memory in which the change in logic states occurs by use of a high voltage, comprising
a control circuit for generating a first detection enable signal in response to a state change signal indicating an intent to change logic states of one or more memory cells in the non-volatile memory; and
a voltage detection circuit for generating a voltage valid signal in response to the first detection enable signal if a voltage at the power supply terminal is above a predetermined voltage; and
prevention means for preventing the high voltage from reaching the non-volatile memory in response to the voltage valid signal not being asserted.
31. The processing unit of claim 30 , wherein the high voltage is generated external to the processing unit and the prevention means blocks the high voltage from reaching the non-volatile memory.
32. The processing unit of claim 30 , wherein the prevention means comprises a charge pump that is disabled in response to the voltage valid signal not being asserted.
33. The processing unit of claim 30 , wherein the control circuit is further characterized as generating the state change signal in response to one of a program signal and an erase signal.
34. The processing unit of claim 33 , further comprising a register for providing a second detection enable signal, wherein the control circuit receives the second detection enable signal and provides the first detection enable signal in response to the second detection enable signal being asserted.
35. The processing unit of claim 34 , wherein the voltage detection circuit is further characterized as generating a voltage low signal in response to the voltage at the power supply terminal being below the predetermined voltage, further comprising logic means for generating a low voltage interrupt signal in response to the voltage low signal.