Semiconductor device having a plurality of different layers and method therefor
View Patent ↗Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
1. A semiconductor device comprising:
a substrate;
a buried layer overlying the substrate and in contact with the substrate, the buried layer comprising a plurality of discrete layers, at least two of the plurality of discrete layers having differing elastic moduli;
a semiconductor layer overlying and in contact with the buried layer;
a first transistor of a first conductivity type having a channel region that is formed within the semiconductor layer and overlying a first region of the buried layer, wherein the first region of the buried layer has a first effective elastic modulus of predetermined value to optimize stress in the channel of the first transistor; and
a second transistor of a second conductivity type having a channel region that is formed within the semiconductor layer and overlying a second region of the buried layer, wherein the second region of the buried layer has a second elastic effective modulus of predetermined value to optimize stress in the channel of the second transistor in a manner different than the first transistor.
2. The semiconductor device of claim 1 wherein the plurality of discrete layers of the buried layer further comprise a plurality of dielectric layers.
3. The semiconductor device of claim 1 wherein the plurality of discrete layers of the buried layer further comprise one or more conductive interior layers.
4. The semiconductor device of claim 3 further comprising:
an electrical contact extending from one of the one or more conductive interior layers to an exposed surface of the semiconductor device.
5. The semiconductor device of claim 1 wherein the first transistor is an N-channel transistor and the first effective elastic modulus has a value that reduces compressive stress or increases tensile stress of the channel of the N-channel transistor.
6. The semiconductor device of claim 1 wherein the second transistor is a P-channel transistor and the second effective elastic modulus has a value that increases compressive stress or reduces tensile stress of the channel of the P-channel transistor.
7. A method of controlling stress in a semiconductor device comprising:
providing a substrate;
providing a buried layer overlying the substrate and in contact with the substrate, the buried layer comprising a plurality of discrete layers, at least two of the plurality of discrete layers having differing elastic moduli;
providing a semiconductor layer overlying and in contact with the buried layer;
providing a first transistor of a first conductivity type having a channel region that is formed within the semiconductor layer and overlying a first region of the buried layer, wherein the first region of the buried layer has a first effective elastic modulus of predetermined value to optimize external stress effects in the channel of the first transistor; and
providing a second transistor of a second conductivity type having a channel region that is formed within the semiconductor layer and overlying a second region of the buried layer, wherein the second region of the buried layer has a second elastic effective modulus of predetermined value to optimize external stress effects in the channel of the second transistor in a manner different than the first transistor.
8. The method of claim 7 further comprising:
forming the plurality of discrete layers of the buried layer with a plurality of dielectric layers.
9. The method of claim 7 further comprising:
forming the plurality of discrete layers of the buried layer with one or more conductive interior layers.
10. The method of claim 9 further comprising:
forming an electrical contact from one of the one or more conductive interior layers to an exposed surface of the semiconductor device.
11. The method of claim 7 further comprising:
forming the first transistor as an N-channel transistor; and
selecting materials of the plurality of discrete layers in the first region to make the first effective elastic modulus have a value that reduces compressive stress or increases tensile stress of the channel of the N-channel transistor.
12. The method of claim 11 further comprising:
modifying one or more of the plurality of discrete layers in the second region to make the second effective elastic modulus have a value that increases compressive stress or decreases tensile stress of the channel region of the second transistor.
13. The method of claim 12 further comprising:
modifying the one or more of the plurality of discrete layers in the second region by etching the one or more of the plurality of discrete layers to remove the one or more of the plurality of discrete layers in the second region; and
replacing the one or more of the plurality of discrete layers in the second region with a desired material to obtain a desired effective elastic modulus.
14. The method of claim 7 further comprising:
forming the first transistor as an P-channel transistor; and
selecting materials of the plurality of discrete layers in the first region to make the first effective elastic modulus have a value that increases compressive stress or reduces tensile stress of the channel of the P-channel transistor.
15. The method of claim 14 further comprising:
modifying one or more of the plurality of discrete layers in the second region to make the second effective elastic modulus have a value that decreases compressive stress or increases tensile stress of the channel region of the second transistor.
16. A method of controlling stress in a semiconductor device comprising:
providing a substrate;
providing a buried layer overlying the substrate and in contact with the substrate, the buried layer comprising a plurality of discrete layers, at least two of the plurality of discrete layers having differing elastic moduli;
providing a semiconductor layer overlying and in contact with the buried layer;
forming a trench defining an area for a first transistor, the trench providing electrical isolation;
etching vertically through a portion of the plurality of discrete layers and etching laterally through at least one of the plurality of discrete layers and using the trench as a lateral etch stop, thereby forming a cavity within a portion of the area for the first transistor;
filling the cavity with a conductive interior layer;
providing a first transistor within the area for the first transistor and having a channel region that is formed within the semiconductor layer and overlying a first region of the buried layer, wherein the first region of the buried layer has a first effective elastic modulus; and
providing a second transistor having a channel region that is formed within the semiconductor layer and overlying a second region of the buried layer, wherein the second region of the buried layer has a second elastic effective modulus of predetermined value to optimize external stress effects in the channel of the second transistor in a manner different than the first transistor.
17. The method of claim 16 further comprising:
making the first elastic effective modulus substantially equal to the second elastic effective modulus.
18. The method of claim 16 further comprising:
forming the first transistor as an N-channel transistor and forming the plurality of discrete layers of the buried layer with materials comprising silicon nitride of sufficient thickness to increase the effective elastic modulus of the buried layer.
19. The method of claim 16 further comprising:
forming the first transistor as a P-channel transistor and forming the plurality of discrete layers of the buried layer with materials comprising a silicated glass of sufficient thickness to reduce the effective elastic modulus of the buried layer.