Electrostatic discharge (ESD) protection circuit for multiple power domain integrated circuit
View Patent ↗An integrated circuit ( 300/400 ) includes first and second power domains and a bank of input/output (I/O) cells ( 305/405 ) coupled to the first and second power domains. The bank of I/O cells ( 305/405 ) includes a first plurality of active clamps ( 374/445 ) for the first power domain and a second plurality of active clamps ( 384/425 ) for the second power domain wherein the first ( 374/445 ) and second ( 384/425 ) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells ( 420, 440 ) has a bonding pad ( 421, 441 ) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element ( 425, 445 ) for a respective second power domain. According to another aspect, each of the plurality of input/output cells ( 420, 440 ) has a bonding pad ( 421, 441 ) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.
1. An integrated circuit comprising:
a first power domain;
a second power domain;
a bank of input/output (I/O) cells coupled to said first and second power domains, including a first plurality of active clamps for said first power domain and a second plurality of active clamps for said second power domain wherein said first and second pluralities of active clamps overlap along said bank of I/O cells.
2. The integrated circuit of claim 1 , wherein each of said first and second pluralities of active clamps operate in parallel to dissipate an ESD event occurring between positive power supply and ground rails of respective ones of said first and second power domains.
3. The integrated circuit of claim 2 , wherein said bank of I/O cells further comprises:
a first plurality of I/O cells each conducting a respective I/O signal referenced to said first power domain; and
a second plurality of I/O cells each conducting a respective I/O signal referenced to said second power domain.
4. The integrated circuit of claim 3 , wherein each of said first plurality of I/O cells comprises:
a first diode coupled between a respective bonding pad and a respective positive power supply rail of said first power domain;
a second diode coupled between a respective ground rail of said first power domain and said respective bonding pad; and
an active clamp coupled between said respective positive power supply rail and said respective ground rail of said first power domain.
5. The integrated circuit of claim 4 , wherein each of said second plurality of I/O cells comprises:
a first diode coupled between a respective bonding pad and a respective positive power supply rail of said second power domain;
a second diode coupled between a respective ground rail of said second power domain and said respective bonding pad; and
an active clamp coupled between said respective positive power supply rail and said respective ground rail of said second power domain.
6. The integrated circuit of claim 3 , wherein each of said first plurality of I/O cells comprises:
a first diode coupled between a respective bonding pad and a respective positive power supply rail of said first power domain;
a second diode coupled between a respective ground rail of said first power domain and said respective bonding pad; and
an active clamp coupled between a respective positive power supply rail and a respective ground rail of said second power domain.
7. The integrated circuit of claim 6 , wherein each of said second plurality of I/O cells comprises:
a first diode coupled between a respective bonding pad and said respective positive power supply rail of said second power domain;
a second diode coupled between said respective ground rail of said second power domain and said respective bonding pad; and
an active clamp coupled between said respective positive power supply rail and said respective ground rail of said first power domain.
8. An integrated circuit comprising:
a plurality of input/output (I/O) cells each having a bonding pad for conducting an I/O signal referenced to a respective first power domain and at least one ESD protection element for a respective second power domain; and
a plurality of conductors for said first and second power domains crossing each of said plurality of I/O cells.
9. The integrated circuit of claim 8 , wherein each of said plurality of I/O cells further comprises:
at least one ESD protection element for said respective first power domain.
10. The integrated circuit of claim 8 , wherein said plurality of I/O cells comprises:
a first I/O cell for conducting an I/O signal referenced to a first power domain and at least one ESD protection element for a respective second power domain; and
a second I/O cell for conducting an I/O signal referenced to said second power domain and at least one ESD protection element for said first power domain.
11. The integrated circuit of claim 8 , wherein said at least one ESD protection element for said respective second power domain comprises an active clamp, and wherein the integrated circuit further comprises trigger circuitry for activating active clamps of said plurality of I/O cells in response to detecting ESD events.
12. The integrated circuit of claim 11 , wherein said active clamp comprises a metal-oxide-semiconductor (MOS) transistor having a first source/drain terminal coupled to a positive power supply voltage rail of said respective second power domain, a gate coupled to said trigger circuitry for receiving a respective trigger signal, and a second source/drain terminal coupled to a negative power supply voltage rail of said respective second power domain.
13. An integrated circuit comprising:
a plurality of input/output (I/O) cells each having a bonding pad for conducting a respective I/O signal and at least one ESD protection element for each of a first power domain and a second power domain; and
a plurality of conductors for said first and second power domains crossing each of said plurality of I/O cells.
14. The integrated circuit of claim 13 , wherein for a first one of said plurality of I/O cells:
said respective output signal is referenced to said first power domain;
said at least one ESD protection element for said first power domain comprises first and second diodes; and
said at least one ESD protection element for said second power domain comprises an active clamp.
15. The integrated circuit of claim 14 , wherein for a second one of said plurality of I/O cells:
said respective output signal is referenced to said second power domain;
said at least one ESD protection element for said first power domain comprises an active clamp;
said at least one ESD protection element for said second power domain comprises first and second diodes.
16. The integrated circuit of claim 15 , wherein said active clamp for each of said first one of said plurality of I/O cells and said second one of said plurality of I/O cells comprises an N-channel metal-oxide-semiconductor (MOS) transistor.
17. The integrated circuit of claim 13 , further comprising:
horizontally extending power supply buses for each of said first and second power domains,
wherein each of said plurality of I/O cells is located adjacent to said horizontally extending power supply buses.
18. The integrated circuit of claim 17 , further comprising:
a power cell located adjacent to said horizontally extending power supply buses, said power cell comprising trigger circuitry for activating an active clamp of each of said first and second I/O cells in response to ESD events.
19. The integrated circuit of claim 18 , wherein said trigger circuitry comprises:
a first trigger circuit having inputs coupled between positive and negative power supply voltage rails of the first power domain, and an output for providing a first trigger signal to activate said active clamp of said second power domain in response to sensing an ESD event in the first power domain; and
a second trigger circuit having inputs coupled between positive and negative power supply voltage rails of the second power domain, and an output for providing a second trigger signal to activate said active clamp of said second power domain in response to sensing an ESD event in the second power domain.
20. The integrated circuit of claim 19 , further comprising:
a first diode having a positive terminal coupled to a bonding pad of said first I/O cell, and a negative terminal coupled to a first boost rail, and
a second diode having a positive terminal coupled to a bonding pad of said second I/O cell, and a negative terminal coupled to a second boost rail,
wherein said first trigger circuit further has an input coupled to said first boost rail and provides said first trigger signal using a voltage on said first boost rail, and
wherein said second trigger circuit further has an input coupled to said first boost rail and provides said second trigger signal further in response to sensing an ESD event on said second boost rail.