IP Library Granted Patent US 8,886,895
Granted Patent B2
US 8,886,895 · App. 10/940,121 · Granted Nov 11, 2014

System and method for fetching information in response to hazard indication information

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Quick Facts
Patent No.
US 8,886,895
App. No.
10/940,121
Granted
Nov 11, 2014
Kind
B2
Abstract

A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

Claims (32)

1. A method for fetching information in response to hazard indication information, the method comprises:

associating hazard indication information with at least one information unit that is being fetched to a cache module;

receiving a request to perform a fetch operation; and

determining whether to fetch the at least one information unit that is requested for fetching in the request to perform the fetch operation, wherein the determining is carried out in response to the hazard indication information and in response to dirty information associated with the at least one information unit; wherein the determining comprises preventing a replacement of an updated information unit stored in the cache module but not stored in a high-level memory module by an information unit retrieved from the high-level memory module.

2. The method of claim 1 wherein the stage of associating comprises storing address information of at least one information unit that is being fetched.

3. The method of claim 2 wherein the stage of determining comprises comparing the stored address information to address information associated with the received request to perform a fetch operation.

4. The method of claim 1 wherein the stage of associating comprises allocating a hazard indication register for each cache line that comprises an information unit that is being fetched, wherein the hazard indication register has a first portion that stores an address of the cache line, and a second portion for storing multiple hazard indication bits, each associated with a single information unit of the cache line.

5. The method of claim 1 wherein the fetch operation comprises a speculative fetch operation.

6. The method of claim 1 wherein the fetch operation comprises fetching at least one information unit from another memory module.

7. The method of claim 1 wherein multiple information units are fetched in fetch bursts.

8. The method of claim 1 wherein speculative information units associated with different mandatory information units are fetched in an interlaced manner.

9. The method of claim 1 wherein the stage of associating comprising assigning at least one hazard indication bit to each information unit that is being fetched.

10. A method for fetching information in response to hazard indication information, the method comprising the stages of:

fetching to a cache module, from a memory module that is not the cache module, a first information unit;

initiating a process of writing an updated information unit to the cache module and to another memory module and updating hazard indication information to reflect a progress of the writing process to the other memory module;

receiving a request to retrieve the updated information unit; and

retrieving the updated information unit in response to the hazard indication information; wherein the retrieving comprises preventing a replacement of the updated information unit stored in the cache module by the first information unit.

11. The method of claim 10 wherein the hazard indication information is associated with address information of at least one information unit that is being fetched.

12. The method of claim 11 wherein the stage of retrieving is responsive to a comparison between the stored address information to address information associated of the updated information unit.

13. The method of claim 10 wherein the stage of updating is preceded by a stage of allocating a hazard indication register for each cache line that comprises an information unit that is being fetched, wherein the hazard indication register has a first portion that stores an address of the cache line, and a second portion for storing multiple hazard indication bits, each associated with a single information unit of the cache line.

14. The method of claim 10 wherein the fetch operation comprises a speculative fetch operation.

15. The method of claim 10 wherein the fetch operation comprises fetching at least one information unit from another memory module.

16. The method of claim 10 wherein multiple information units are fetched in fetch bursts.

17. The method of claim 10 wherein speculative information units associated with different mandatory information units are fetched in an interlaced manner.

18. An apparatus for fetching information in response to hazard indication information, the apparatus comprises:

a cache module;

hazard indication logic for associating hazard indication information to at least one information unit that is being fetched to the cache module; and

a controller, coupled to the hazard information logic and to the cache module, for determining whether to initiate a fetch operation for at least one information unit that is requested for fetching in a request to perform the fetch operation, wherein the controller is configured to determine whether to initiate the fetch operation in response to the hazard indication information and in response to dirty information associated with the at least one information unit; wherein the controller is adapted to prevent a replacement of an updated information unit stored in the cache module by a corresponding non-updated information unit being fetched to the cache module.

19. The apparatus of claim 18 wherein the controller is further responsive to cache miss events.

20. The apparatus of claim 18 wherein the controller is adapted to determine to initialize speculative fetch operations.

21. The apparatus of claim 18 wherein the hazard indication logic comprises at least one hazard indication register, wherein the hazard indication register has a first portion that stores an address of the cache line, and a second portion for storing multiple hazard indication bits, each associated with a single information unit of the cache line.

22. The apparatus of claim 18 wherein the hazard indication register comprises multiple hazard indication registers, each associated with a cache line that comprises at least one information unit that is being fetched, wherein each hazard indication register has a first portion that stores an address of the cache line, and a second portion for storing multiple hazard indication bits, each associated with a single information unit of the cache line.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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