Ground shields for semiconductors
View Patent ↗A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.
1. A ground shield for a semiconductor device of the type that includes a set of conductive wires, comprising:
a first metal layer on a semiconductor body, the first layer comprising a series of regularly spaced apart lateral first slots therein; and
a second metal layer above the first metal layer, the second layer comprising a series of regularly spaced apart lateral second slots therein, the second slots overlying spaces between the first slots, and the second metal layer overlying the first slots;
wherein each of the first and second metal layers are electrically contiguous and are positioned over the set of conductive wires such that the first and second metal layers form the ground shield with respect to the conductive wires.
2. The ground shield of claim 1 , wherein the second slots comprise therein islands of an interlevel dielectric ILD 1 , the islands laid on the first metal layer.
3. The ground shield of claim 1 , wherein the first slots comprise therein islands of an interlevel dielectric ILD 0 , the ILD 0 islands having a width Y 1 .
4. The ground shield of claim 3 , wherein an ILD 0 island is overlaid by an island of ILD 1 having a width of Y 2 , where Y 2 is greater than or equal to Y 1 .
5. The ground shield of claim 1 , wherein a contact area of the first metal layer on a semiconductor body is less than about sixty percent based on the ground shield area.
6. The ground shield of claim 1 , wherein a via area of the second metal layer on the first metal layer is less than about forty percent based on the ground shield area.
7. The ground shield of claim 1 , wherein the area of the ground shield is greater than about five square millimeters.
8. A semiconductor device comprising:
a semiconductor body;
an inboard wire pad located on the semiconductor body and extending along a length of the device;
an outboard wire pad located on the semiconductor body, extending along a length of the device, the outboard pad spaced further from a longitudinal axis of the chip than the inboard pad; and
a ground shield located between the inboard and outboard pad, the ground shield extending along a length of the device, the ground shield comprising:
a first metal layer on the semiconductor body, the first layer comprising a series of regularly spaced apart lateral first slots therein; and
a second metal layer above the first metal layer, the second layer comprising a series of regularly spaced apart lateral second slots therein, the second slots overlying spaces between the first slots, and the second metal layer overlying the first slots.
9. The device of claim 8 , further comprising a wire extending over the ground shield, from the inboard pad to the outboard wire pad, substantially parallel to slots in the first and second metal layers.
10. The device of claim 9 , wherein slotted patterning of the first and second metal layers form a repeating unit of the ground shield.
11. The device of claim 8 , wherein the second slots comprise therein interlevel dielectric ILD 1 , the ILD 1 laid on the first metal layer.
12. The device of claim 8 , wherein first slots comprise therein islands of interlevel dielectric ILD 0 , each island of ILD 0 having a width Y 1 .
13. The device of claim 12 , wherein ILD 0 islands are overlaid with islands of ILD 1 , each ILD 1 island having a width of Y 2 , where Y 2 is greater than or equal to Y 1 .
14. The device of claim 8 , wherein a contact area of the first metal layer on a semiconductor body is less than is less than about sixty percent based on the ground shield area.
15. The device of claim 8 , wherein a via area of the second metal layer on the first metal layer is less than about forty percent based on the ground shield area.
16. The device of claim 8 , wherein the area of the ground shield is greater than about five square millimeters.
17. The device of claim 8 , wherein the device comprises an RF LDMOS chip.
18. The device of claim 17 , wherein the device further comprises a highly doped implant layer under the ground shield and a back-side ground.