Method of forming a substrateless semiconductor package
View Patent ↗A method of forming a substrateless semiconductor package ( 10 ) includes forming a carrier ( 16 ) on a base plate ( 12 ) and attaching an integrated circuit (IC) die ( 32 ) to the carrier ( 16 ). The IC die ( 32 ) then is electrically connected to the carrier ( 16 ). A molding operation is performed to encapsulate the IC die ( 32 ), the electrical connections ( 36 ) and the carrier ( 16 ). Thereafter, the base plate ( 12 ) is removed.
1. A method of forming a semiconductor package, the method comprising:
providing a base plate having a plurality of cavities;
forming a carrier on the base plate with a solder material, wherein the solder material fills the plurality of cavities thereby forming a plurality of pillars;
placing an integrated circuit (IC) die on the carrier;
electrically connecting the IC die and the carrier;
performing a molding operation to encapsulate the IC die, the electrical connections and at least a portion of the carrier; and
removing the base plate after performing the molding operation, wherein distal ends of the pillars are exposed.
2. The method of forming a semiconductor package of claim 1 , wherein the solder material is printed on the base plate in two passes.
3. The method of forming a semiconductor package of claim 2 , wherein the solder material is one of a eutectic solder, high lead solder and a lead free solder.
4. The method of forming a semiconductor package of claim 2 , wherein the solder material is printed on the base plate with a stencil.
5. The method of forming a semiconductor package of claim 4 , wherein the stencil has a thickness of less than about 4 mils.
6. The method of forming a semiconductor package of claim 1 , wherein the base plate is made of a material that is separable from the solder material.
7. The method of forming a semiconductor package of claim 6 , wherein the base plate material is one of graphite, aluminum and stainless steel.
8. The method of forming a semiconductor package of claim 7 , wherein the base plate has a thickness of less than about 1 millimeters (mm).
9. The method of forming a semiconductor package of claim 8 , wherein each of the plurality of cavities has a depth of about 0.40 mm.
10. A method of forming a semiconductor package, comprising:
providing a base plate having a plurality of cavities;
forming a carrier on the base plate with a solder material, wherein the solder material fills the plurality of cavities thereby forming a plurality of solder pillars;
attaching an integrated circuit (IC) die on the carrier;
electrically connecting bonding pads of the IC die with respective ones of the solder pillars that surround the IC die;
performing a molding operation to encapsulate the IC die, the electrical connections and a portion of the carrier; and
reflowing the plurality of pillars to form a plurality of solder globules.
11. The method of forming a semiconductor package of claim 10 , wherein controlled collapse chip carrier connection (C 5 ) type interconnections are formed from the plurality of solder globules.
12. The method of forming a semiconductor package of claim 1 , wherein the electrical connection between the IC die and the carrier is by wire bonding.
13. The method of forming a semiconductor package of claim 1 , wherein the IC die is attached to the carrier using an adhesive tape.
14. The method of forming a semiconductor package of claim 13 , wherein a standoff of about 0.075 mm is maintained between opposing surfaces of the adhesive tape and the base plate.
15. The method of forming a semiconductor package of claim 1 , wherein the electrical connection between the IC die and the carrier is by flip chip bonding.
16. The method of forming a semiconductor package of claim 10 , further comprising the step of removing the base plate after performing the molding operation such that distal ends of the pillars are exposed.
17. A method of forming a plurality of semiconductor packages, comprising:
providing a base plate having a plurality of cavities;
forming a carrier on the base plate with a solder material, wherein the solder material fills the plurality of cavities thereby forming a plurality of pillars;
placing a plurality of integrated circuit (IC) dies on the carrier;
electrically connecting the IC dies with respective ones of the plurality of pillars;
performing a molding operation to encapsulate the IC dies, the electrical connections and at least a portion of the carrier; and
removing the base plate to expose distal ends of the pillars; and
performing a singulating operation to separate adjacent ones of the plurality of IC dies, thereby forming a plurality of semiconductor packages.