Coherent access register data transfer device and methods thereof
View Patent ↗Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
1. A method, comprising:
receiving at a first time a first write request comprising a first data and a first address value, wherein the first address value is received at a first set of address nodes;
determining if the first address value is associated with one of a plurality of coherent access registers, wherein each one of the plurality of coherent access registers is to receive data from a plurality of write requests simultaneously;
storing, in response to determining that the first address value is associated with a first register of the plurality of coherent access registers, the first data at a latch coupled to each of the plurality of coherent access registers;
receiving at a second time after the first time a second write request comprising a second data and a second address value, wherein the second address value is received at the first set of address nodes;
storing the second data at a second register while maintaining the first data at the latch in response to determining the second address value is not associated with any of the plurality of coherent access registers;
receiving at a third time after the second time a third write request comprising a third data and a third address value, wherein the third address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the third address value is associated with the first register of the plurality of coherent access registers, the first data stored at the latch and the third data at the first register of the plurality of coherent access registers.
2. The method of claim 1 , further comprising:
receiving at a fourth time a fourth write request comprising a fourth data and a fourth address value, wherein the fourth address value is received at the first set of address nodes;
storing, in response to determining that the fourth address value is associated with a second register of the plurality of coherent access registers, the fourth data at the latch;
receiving at a fifth time a fifth write request comprising a fifth data and a fifth address value, wherein the fifth address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the fifth address value matches the fourth address value, the fourth data stored at the latch and the fifth data at the second register of the plurality of coherent access registers.
3. The method of claim 1 , further comprising storing, in response to determining that the third address value is not associated with the first register of the plurality of coherent access registers, the third data at the latch.
4. The method of claim 3 , further comprising:
receiving at a fourth time a fourth write request comprising a fourth data and a fourth address value, wherein the fourth address value is received at the first set of address nodes;
simultaneously storing, in response to determining that the fourth address value is associated with a second register of the plurality of coherent access registers, the data stored at the latch and the fourth data at a second of the plurality of coherent access registers.
5. The method of claim 3 , wherein the third data is stored at the latch in response to determining that the third address value is associated with one of the plurality of coherent access registers.
6. The method of claim 5 , further comprising storing, in response to determining that the third address value is not associated with one of the plurality of coherent access registers, the third data at a third register associated with the third address value, wherein the third register is not one of the plurality of coherent access registers.
7. The method of claim 1 , further comprising latching the first address value at an address register in response to determining that the first address value is associated with one of the plurality of coherent access registers.
8. The method of claim 1 , further comprising:
receiving at a fourth time a fourth write request comprising a fourth data and a fourth address value, wherein the fourth address value is received at the first set of address nodes;
determining if the fourth address value is associated with one of the plurality of coherent access registers;
storing, in response to determining that the fourth address value is associated with a third register of the plurality of coherent access registers, the fourth data at the latch;
receiving at a fifth time a fifth write request comprising a fifth data and a fifth address value, wherein the fifth address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the fifth address value matches the fourth address value, the fourth data stored at the latch and the fifth data at the third register of the plurality of coherent access registers.
9. The method of claim 8 , further comprising storing, in response to determining that the fourth address value is not associated with the third register of the plurality of coherent access registers, the fourth data at the latch.
10. The method of claim 9 , further comprising:
receiving at a sixth time a sixth write request comprising a sixth data and a sixth address value, wherein the sixth address value is received at the first set of address nodes;
simultaneously storing, in response to determining that the sixth address value is associated with a fourth register of the plurality of coherent access registers, the data stored at the latch and the sixth data at the fourth register of the plurality of coherent access registers.
11. The method of claim 9 , wherein the fifth data is stored at the latch in response to determining that the fifth address value is associated with one of the plurality of coherent access registers.
12. A method, comprising:
receiving at a peripheral device at a first time a first write request comprising a first data and a first address value, wherein the first address value is received at a first set of address nodes from a bus master device;
receiving the first data at the peripheral device via a data bus coupled between the bus master device and the peripheral device;
determining if the first address value is associated with one of a plurality of coherent access registers at the peripheral device, wherein a size of a first register of the plurality of coherent access registers larger than a size of the data bus;
storing, in response to determining that the first address value is associated with the first register of the plurality of coherent access registers, the first data at a latch of the peripheral device coupled to each of the plurality of coherent access registers;
receiving at a second time a second write request comprising a second data and a second address value, wherein the second address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the second address value is associated with the first register of the plurality of coherent access registers, the first data stored at the latch and the second data at the first register of the plurality of coherent access registers without storing the second data at the latch.
13. The method of claim 12 , further comprising:
receiving at a third time a third write request comprising a third data and a third address value, wherein the third address value is received at the first set of address nodes;
determining if the third address value is associated with one of the plurality of coherent access registers;
storing, in response to determining that the third address value is associated with a second register of the plurality of coherent access registers, the third data at the latch;
receiving at a fourth time a fourth write request comprising a fourth data and a fourth address value, wherein the fourth address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the fourth address value matches the third address value, the third data stored at the latch and the fourth data at the second register of the plurality of coherent access registers.
14. The method of claim 12 , further comprising storing, in response to determining that the second address value is not associated with the first register of the plurality of coherent access registers, the second data at the latch.
15. The method of claim 14 , further comprising:
receiving at a third time a third write request comprising a third data and a third address value, wherein the third address value is received at the first set of address nodes;
simultaneously storing, in response to determining that the third address value is associated with a second register of the plurality of coherent access registers, the data stored at the latch and the third data at a second of the plurality of coherent access registers.
16. A method, comprising:
receiving at a first time a first write request comprising a first data and a first address value, wherein the first address value is received at a first set of address nodes;
determining if the first address value is associated with one of a plurality of coherent access registers, wherein each one of the plurality of coherent access registers is to receive data from a plurality of write requests simultaneously;
storing, in response to determining that the first address value is associated with a first register of the plurality of coherent access registers, the first data at a latch coupled to each of the plurality of coherent access registers;
receiving at a second time after the first time a second write request comprising a second data and a second address value, wherein the second address value is received at the first set of address nodes;
storing the second data at a second register while maintaining the first data at the latch in response to determining the second address value is not associated with any of the plurality of coherent access registers;
receiving at a third time after the second time a third write request comprising a third data and a third address value, wherein the third address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the third address value matches the first address value, the first data stored at the latch and the third data at the first register of the plurality of coherent access registers.
17. The method of claim 16 , further comprising:
receiving at a fourth time a fourth write request comprising a fourth data and a fourth address value, wherein the fourth address value is received at the first set of address nodes;
determining if the fourth address value is associated with one of the plurality of coherent access registers;
storing, in response to determining that the fourth address value is associated with a second register of the plurality of coherent access registers, the fourth data at the latch;
receiving at a fifth time a fifth write request comprising a fifth data and a fifth address value, wherein the fifth address value is received at the first set of address nodes; and
simultaneously storing, in response to determining that the fifth address value matches the fourth address value, the fourth data stored at the latch and the fifth data at the second register of the plurality of coherent access registers.
18. The method of claim 16 , further comprising storing, in response to determining that the third address value does not match the first address, the third data at the latch.
19. The method of claim 18 , further comprising:
receiving at a fifth fourth time a fourth write request comprising a fourth data and a fourth address value, wherein the fourth address value is received at the first set of address nodes;
simultaneously storing, in response to determining that the fourth address value is associated with a second register of the plurality of coherent access registers, the data stored at the latch and the fourth data at a second of the plurality of coherent access registers.