Low profile semiconductor device having improved heat dissipation
View Patent ↗A package substrate ( 12, 52 ) has a first surface, a second surface opposite a first surface, and a cavity ( 22, 70 ) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die ( 20, 60 ) is placed in the cavity, and a conductive material ( 24, 72 ) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer ( 28, 78 ) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.
1. A semiconductor device comprising:
a package substrate having a first surface, a second surface opposite the first surface, and a cavity formed in the first surface and extending into the package substrate, the cavity having a cavity wall substantially perpendicular to the first and second surfaces;
an integrated circuit die, wherein at least a portion of the integrated circuit die is in the cavity, and wherein the integrated circuit die has a first surface, a second surface opposite the first surface, an outer wall substantially perpendicular to the first and second surfaces, a ledge portion at an intersection of the first surface of the integrated circuit die and the outer wall, wherein at least a portion of the outer wall substantially faces the cavity wall; and
a conductive material in the cavity, wherein the conductive material thermally couples the outer wall of the integrated circuit die to the cavity wall.
2. The semiconductor device of claim 1 , further comprising:
an encapsulation layer overlying the first surface of the integrated circuit die, the conductive material, and at least a portion of the first surface of the package substrate.
3. The semiconductor device of claim 2 , wherein the encapsulation layer comprises a material different from the conductive material.
4. The semiconductor device of claim 2 , wherein a thermal conductivity of the conductive material is greater than a thermal conductivity of the encapsulation layer.
5. The semiconductor device of claim 1 , wherein the conductive material substantially fills the cavity between the outer wall of the integrated circuit die and the cavity wall.
6. The semiconductor device of claim 1 , wherein the integrated circuit die is entirely within the cavity.
7. The semiconductor device of claim 1 , further comprising:
a plurality of wire bonds extending from the first surface of the integrated circuit die to the first surface of the package substrate.
8. The semiconductor device of claim 1 , wherein at least a portion of the cavity wall is plated with a second conductive material.
9. The semiconductor device of claim 8 , wherein the cavity wall of the package substrate comprises a plurality of cut-out portions.
10. The semiconductor device of claim 1 , wherein the package substrate comprises a solder mask ridge near an intersection of the first surface of the package substrate and the cavity wall.
11. The semiconductor device of claim 1 , wherein the cavity extends through the package substrate from the first surface of the package substrate to the second surface of the package substrate.
12. The semiconductor device of claim 11 , wherein the second surface of the integrated circuit die is substantially coplanar with the second surface of the package substrate.
13. The semiconductor device of claim 11 , wherein the second surface of the integrated circuit die is capable of being coupled to a printed circuit board.
14. The semiconductor device of claim 1 , wherein the conductive material bonds the outer wall of the integrated circuit die to the cavity wall.