Front-end method for NICAM encoding
View Patent ↗A NICAM encoding method comprises performing NICAM processing and coupling a front-end to the NICAM processing. The front-end processing operates with a system clock that is integer divisible such that the system clock can be used by both the NICAM processing and the front-end processing. The front-end processing includes a front-end input processing and a front-end output processing. The front-end input processing is coupled to an input of the NICAM processing and the front-end output processing is coupled to an output of the NICAM processing.
1. A NICAM encoding method comprising:
performing NICAM processing; and
coupling front-end processing to the NICAM processing, wherein the front-end processing synchronizes the front-end processing and the NICAM processing with timing derived from integer divisions of a single system clock, wherein the front-end processing comprises a front-end input processing and a front-end output processing, the front-end input processing being coupled to an input of the NICAM processing and the front-end output processing being coupled to an output of the NICAM processing, and wherein the front-end input processing comprises one of:
(a) use of an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator, or
(b) use of a dual-channel analog-to-digital converter (ADC), an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the ADC couples to the interpolator, the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator.
2. The NICAM encoding method of claim 1 , wherein the NICAM processing operates at a sampling frequency of 728 kHz or 364 kHz, and wherein the front-end processing comprises a front-end input processing that has an output at a sampling frequency of 32 kHz and a front-end output processing that has an output at a sampling frequency of one of 24 MHz or 27 MHz.
3. The NICAM encoding method of claim 1 , further wherein the NICAM processing and the front-end processing are embedded within an audio/video integrated circuit.
4. The NICAM encoding method of claim 1 , further comprising:
using a first analog filter coupled to an input of the front-end processing, wherein the first analog filter comprises an anti-aliasing filter; and
using a second analog filter coupled to an output of the front-end processing, wherein the second analog filter comprises a reconstruction filter.
5. The NICAM encoding method of claim 1 , further wherein the quantity (N/(M*P)) is equal to a ratio of 32 kHz to the system clock.
6. The NICAM encoding method of claim 1 , further wherein the dual-channel ADC includes an initial resolution of better than 14 bits and provides an output of the front-end input processing with a resolution of 14 bits.
7. The NICAM encoding method of claim 1 , further wherein the pre-emphasis filter operates at a frequency greater than 32 kHz.
8. The NICAM encoding method of claim 1 , wherein the front-end output processing comprises use of a digital square-root raised-cosine (SRRC) filter with interpolation factor K, a variable interpolator with variable interpolation factor L, a digital mixer, a digital-to-analog converter (DAC), and a sine & cosine generator, wherein the SRRC filter couples to the variable interpolator, the variable interpolator couples to the mixer, and the mixer couples to the DAC and to the sine & cosine generator.
9. The NICAM encoding method of claim 8 , wherein the front-end output processing further comprises use of an interpolator timing circuit, wherein the interpolator timing circuit couples to the SRRC filter, the variable interpolator, and the NICAM processing, further wherein the interpolator timing circuit provides strobes to the NICAM processing, the SRRC filter, and variable interpolating with the variable interpolator.
10. The NICAM encoding method of claim 9 , further wherein the strobe to the NICAM processing approximates one of a 728 kHz or 364 kHz clock derived from the system clock.
11. The NICAM encoding method of claim 9 , further wherein the interpolator timing circuit generates a first strobe signal for the NICAM processing and the SRRC filtering and generates a second strobe signal for the SRRC filtering and the variable interpolating.
12. The NICAM encoding method of claim 11 , wherein the interpolator timing circuit includes an N-bit adder that comprises full adders, wherein N is a prescribed number of bits.
13. The NICAM encoding method of claim 12 , further wherein the N-bit adder includes a 24 bit adder of full adders (FA 0 , FA 1 , . . . , FA 20 , FA 21 , FA 22 , and FA 23 ).
14. The NICAM encoding method of claim 13 , further wherein the first strobe signal corresponds to a MSB Full-adder carry-out (CO 23 ) and the second strobe signal corresponds to a MSB-2 Full-adder carry-out (CO21).
15. The NICAM encoding method of claim 9 , further wherein the interpolator timing circuit provides a strobe for synchronizing the NICAM processing with the front-end output processing by resetting an interpolator timing circuit register of the interpolator timing circuit at regular intervals.
16. The NICAM encoding method of claim 8 , wherein the SRRC filtering with interpolation factor K comprises a pulse shape filtering portion and an interpolating portion, further wherein the pulse shape filtering portion and the interpolating portion are performed individually or as a single combined function.
17. The NICAM encoding method of claim 1 , further wherein the NICAM processing and the front-end processing are performed via a single integrated circuit chip implementation.
18. A NICAM encoding method comprising:
performing a front-end input processing, wherein the front-end input processing comprises one of:
(a) use of an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator, or
(b) use of a dual-channel analog-to-digital converter (ADC), an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the ADC couples to the interpolator, the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator;
performing NICAM processing, the front-end input processing being coupled to an input of the NICAM processing; and
performing front-end output processing, the NICAM processing being coupled to an input of the front-end output processing, wherein the front-end output processing provides a synchronization strobe to the NICAM processing with timing derived from integer divisions of a single system clock.