Granted Patent B2

US 6,864,135 · App. 10/285,374 · Granted Mar 8, 2005

Abstract

Claims (36)

1. A semiconductor fabrication process, comprising:

forming a first gate over a first portion of a semiconductor substrate and a second gate over a second portion of the substrate;

depositing a spacer film over the substrate and the first and second gates; and

forming first spacers on sidewalls of the first gate by etching the spacer film with a first spacer etch and forming second spacers on sidewalls of the second gate by etching the spacer film with a second spacer wherein the first spacer etch is characterized as being more anisotropic than the second spacer etch, wherein the difference in isotropy between the first and second etches causes the first and second spacers to have different widths.

2. The method of claim 1 , further comprising:

forming first source/drain regions in the substrate laterally disposed on either side of the first spacers; and

forming second source/drain regions in the substrate laterally disposed on either side of the second spacers.

3. The method of claim 1 , wherein forming the first and second spacers comprises:

masking the first portion of the substrate with a first spacer mask;

etching portions of the spacer film exposed by the first spacer mask using the first spacer etch;

masking the second portion of the substrate with a second spacer mask;

etching portions of the spacer fin exposed by the second spacer mask using the second spacer etch.

4. The method of claim 3 , wherein the first spacer etch process is further characterized as having an anisotropy of at least 0.9 and the second spacer etch process is further characterized as having an anisotropy of at most 0.7.

5. The method of claim 1 , wherein the first spacer etch process comprises a magnetically enhanced plasma etch process having a first RF energy and the second spacer etch process comprises a non-magnetically enhanced plasma etch process having a second RF energy, where the first RF energy is greater than the second RF energy.

6. The method of claim 3 , wherein the first spacer etch mask is used as a mask for a first source/drain implant and the second spacer etch mask is used as a mask for a second source/drain implant.

7. The method of claim 6 , wherein the first spacer etch mask exposes portions of the substrate containing p-channel transistors and the second spacer etch mask exposes portions of the substrate containing n-channel transistors.

8. The method of claim 3 , wherein the first spacer etch mask and the second spacer etch mask are substantially mirror images of each other.

9. The method of claim 3 , wherein the first and second spacer etch masks both mask at least some common portions of the spacer film.

10. The method of claim 9 , wherein the common portions masked by the first and second spacer etch mask comprise regions of the spacer film overlying high resistivity regions of a polysilicon film wherein the first and second spacer etch mas prevent silicidation of the high resistivity regions of the polysilicon film having higher resistivity than remaining portions of the gate layer film.

11. The method of claim 1 , wherein depositing the spacer film comprises depositing silicon nitride.

12. The method of claim 1 , wherein the first gate is characterized as a p-channel transistor gate and the second gate is characterized as an n-channel transistor gate.

13. The method of claim 12 , further comprising:

forming p-channel and n-channel extension implant regions displaced on either side of the corresponding gate prior to forming the first and second spacers; and

forming p-channel and n-channel source/drain implant regions displaced on either side of the corresponding gate after forming the first and second spacers respectively;

wherein the first spacers are wider than the second space and wherein an extension length of p-channel transistors is longer than an extension length of nchanmel transistors.

14. An integrated circuit fabricated according to the method of claim 1 .

15. A semiconductor fabrication method, comprising

forming a gate of a first transistor over a first portion of a semiconductor substrate and a gate of a second transistor over a second portion of a semiconductor substrate;

depositing a spacer film over the substrate and the transistor gates; and

etching a first portion of the spacer film with a first etch process and etching a second portion of the space film with a second etch process, wherein the anisotropy of the first etch process is greater than the anisotropy of the second etch process and wherein a width of a spacer resulting from the first etch process is greater than a width or a spacer resulting form the second etch process.

16. The method of claim 15 , further comprising:

forming first and second extension implant regions displaced on either side of the first and second transistor gates prior to forming the relatively wide and narrow spacers; and

forming first and second source/drain implant regions displaced on either side of the first and second transistor gates, respectively after forming the wide and narrow spacers wherein an extension length of the first transistor is longer than an extension length of the second transistor.

17. The method of claim 15 , wherein the first transistor is further characterized as a pi channel transistor and the second transistor is further characterized as an n-channel transistor.

18. The method of claim 15 , further comprising, masking the second portion of the spacer film during the etching of the first portion of the film and masking the first portion of the spacer film during the etching of the second portion.

19. The method of claim 18 , further comprising, implanting a first source/drain impurity following the first etch before removing the second portion mask and implanting a second source/drain impurity following the second etch before removing the first portion mask wherein the fist and second masks both serve as a spacer etch mask and an implant mask.

Assignments (17)