Non-volatile memory architecture and method thereof
View Patent ↗A memory array of one-transistor (1T) SONOS bit cells in a common-source architecture is used in conjunction with a reverse read technique to reduce the effect of read disturb. Bit line voltage in the array, during read operation, is constrained to a Vt or less, relative to the control gate, so that read disturb is limited. When information is programmed into a bit cell in the array, the bit line is used as a drain, which has the effect of concentrating charge toward the bitline end of the SONOS transistor. When information is read from a bit cell in the array, the bit line of the selected bit cell is used as a source, instead of a drain. That reversal gives a larger Vt contrast between a 0 and a 1 than a forward read, for a given amount of stored charge. Using the bit line in this manner limits the electric field to which the oxide of the bit cell is exposed, thereby lessening the amount of read disturb, while also improving the magnitude of the read mode signal and, therefore, improving overall tolerance of the read disturb effect.
1. A method comprising:
applying a first voltage to a gate of a bitcell to be read;
applying the first voltage to a first current electrode of the bitcell;
applying a second voltage to a bulk of the bitcell; and
applying a third voltage to a second current electrode of the bitcell, wherein the third voltage is chosen to have a magnitude less than the magnitude of the first voltage to allow a detectable amount of current to flow through the second current electrode when the bitcell is discharged to a low voltage threshold state.
2. The method as in claim 1 , wherein the method of applying the third voltage is constrained to be within a voltage threshold of the first voltage.
3. The method as in claim 2 , wherein the first voltage is a power supply voltage.
4. The method as in claim 1 , wherein the first voltage and the third voltage are obtained from a single supply.
5. The method as in claim 1 , wherein the bitcell is a SONOS non-volatile memory bitcell.
6. The method as in claim 1 , further comprising programming the bitcell using a hot-carrier injection technique.
7. The method as in claim 1 , further comprising erasing the bitcell using a Fowler/Nordheim technique.
8. The method as in claim 1 , wherein applying the third voltage comprises applying the third voltage through a column select transistor having a low-voltage gate dielectric.
9. The method as in claim 8 , wherein applying first voltage comprises applying the first voltage through a wordline select transistor having a high-voltage gate dielectric.
10. The method of claim 1 , wherein applying first voltage comprises applying the first voltage through a wordline select transistor having a high-voltage gate dielectric.
11. A method comprising:
setting a voltage threshold state of a memory cell to a first charge state by supplying charge to the memory cell through a first current electrode of the memory cell; and
reading the first charge state of the memory cell comprises receiving a detectable amount of charge at the first current electrode from the memory cell when the memory cell has the voltage threshold at the first charge state.
12. The method as in claim 11 , wherein the voltage applied to a second current electrode is greater than a voltage applied to the first current electrode.
13. The method as in claim 11 , wherein the memory cell is a SONOS non-volatile memory bitcell.
14. The method as in claim 11 , wherein setting the voltage threshold state of the memory cell comprises programming the memory cell using a hot-carrier injection technique.
15. The method as in claim 11 , wherein setting further comprises erasing the memory cell using a Fowler/Nordheim technique.