IP Library Granted Patent US 7,619,464
Granted Patent B2
US 7,619,464 · App. 11/460,732 · Granted Nov 17, 2009

Current comparison based voltage bias generator for electronic data storage devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,619,464
App. No.
11/460,732
Granted
Nov 17, 2009
Kind
B2
Abstract

An electronic data storage system uses current comparison to generate a voltage bias. In at least one embodiment, a voltage bias generator, that includes a current differential amplifier, generates a current that charges a load to a predetermined voltage bias level. The current comparison results in the comparison between two currents, I ref and I saref . The current I saref can be generated using components that match components in the load and memory circuits in the system. In one embodiment, multiple sense amplifiers represent the load. By using matched components, as physical characteristics of the load and memory circuits change, the current I saref also changes. Thus, the voltage bias changes to match the changing characteristics of the load and memory circuits. The voltage bias generator can include a current booster that decreases the initial charging time of a reactive load.

Claims (65)

1. A system comprising:

a voltage bias generator to generate a voltage bias for a load from a comparison between a first current and a second current, wherein the voltage bias generator further comprises:

a feedback path to receive a feedback signal to alter the first current based on a value of the feedback signal; and

a current booster to supply boost current to the load to decrease an amount of time for the load to reach a predetermined voltage bias level.

2. The system of claim 1 wherein the load comprises a plurality of sense amplifiers coupled to the voltage bias generator, the system further comprising:

a plurality of memory cells coupled to the sense amplifiers.

3. The system of claim 1 wherein the load comprises sense amplifier components and the voltage bias generator further comprises:

a current differential amplifier to compare the first current to the second current and to generate a difference current, wherein the difference current comprises a reference current minus a sense amplifier reference current, wherein during operation of the system the sense amplifier reference current varies in accordance with changes in components that model the sense amplifier components of the load.

4. The system of claim 2 wherein the voltage bias generator further comprises:

a sense amplifier model circuit to generate a current component of the first current, wherein components of the sense amplifier model circuit track one or more change in electrical properties of the sense amplifiers due to environmental changes.

5. The system of claim 1 wherein the load includes a reactive impedance.

6. The system of claim 5 further comprising:

one or more switches coupled to the current booster to stop and start the supply of the boost current to the load.

7. The system of claim 1 wherein the feedback signal comprises the voltage bias.

8. The system of claim 2 wherein the memory cells comprise flash memory cells.

9. An electronic data storage system comprising:

a load;

a first current generator to generate a first current;

a second current generator to generate a second current;

a current differential amplifier, coupled to the load and the first and second current generators, to compare the first current and the second current and to generate an output current to charge the load to a predetermined voltage reference bias;

a feedback path coupled to the first current generator to supply a feedback signal to the first current generator to alter the first current based on a value of the feedback signal;

a current boost source; and

a switch coupled between the current boost source and the second current generator.

10. The electronic data storage system of claim 9 wherein the feedback signal comprises the voltage reference bias.

11. The electronic data storage system of claim 9 wherein the first current generator comprises a sense amplifier model circuit, wherein components of the sense amplifier model circuit track one or more changes in electrical properties of sense amplifiers in the load due to environmental changes.

12. The electronic data storage system of claim 9 wherein the load comprises a plurality of sense amplifiers, the electronic data storage system further comprising:

a plurality of memory cells, each coupled to a respective one of the sense amplifiers.

13. The electronic data storage system of claim 12 wherein the memory cells comprise flash memory cells.

14. A method of generating a voltage reference bias in an electronic data storage system, the method comprising:

generating a first current reference signal;

generating a second current reference signal;

charging a load to a predetermined level of the voltage reference bias using a difference between the first current reference signal and the second current reference signal; and

boosting the second current reference signal by a factor of N, wherein N is a real number greater than one (1).

15. The method of claim 14 wherein the load includes a plurality of sense amplifiers, wherein generating the first current reference signal comprises:

generating a sense amplifier reference current that varies in accordance with changes in modeled sense amplifier components.

16. The method of claim 15 further comprising:

responding to changes in the sense amplifier reference current to maintain the predetermined voltage reference level.

17. The method of claim 14 wherein boosting the second current reference signal by a factor of N further comprises:

during initialization of the electronic data storage system, boosting the second current reference signal by the factor of N, wherein N is a real number greater than one (1).

18. The method of claim 14 wherein the charging a load to a predetermined voltage reference level further comprises:

charging a plurality of input terminals of respective sense amplifiers to the predetermined voltage reference level.

19. The method of claim 14 further comprising:

receiving a feedback signal to alter the first current reference signal based on a value of the feedback signal.

20. An electronic data storage system comprising:

a voltage bias generator to generate a voltage bias for a load from a comparison between a first current and a second current, wherein the voltage bias generator further comprises a feedback path to receive a feedback signal to alter the first current based on a value of the feedback signal and the second current is generated by a constant current source during operation of the electronic data storage system wherein the load includes a reactive impedance and the voltage bias generator further comprises a current booster to supply boost current to the load to decrease an amount of time for the load to reach a predetermined voltage bias level.

21. The electronic data storage system of claim 20 wherein the load comprises a plurality of sense amplifiers coupled to the voltage bias generator, the electronic data storage system further comprising:

a plurality of memory cells coupled to the sense amplifiers.

22. The electronic data storage system of claim 21 wherein the voltage bias generator further comprises:

a sense amplifier model circuit to generate a current component of the first current, wherein components of the sense amplifier model circuit track one or more changes in electrical properties of the sense amplifiers due to environmental changes.

23. The electronic data storage system of claim 21 wherein the memory cells comprise flash memory cells.

24. The electronic data storage system of claim 20 wherein the load comprises sense amplifier components and the voltage bias generator further comprises:

a current differential amplifier to compare the first current to the second current and to generate a difference current, wherein the difference current comprises a reference current minus a sense amplifier reference current, wherein during operation of the electronic data storage system the sense amplifier reference current varies in accordance with changes in components that model the sense amplifier components of the load.

25. The electronic data storage system of claim 20 further comprising:

one or more switches coupled to the current booster to stop and start the supply of the boost current to the load.

26. An electronic data storage system comprising:

a voltage bias generator to generate a voltage bias for a load from a comparison between a first current and a second current, wherein:

the voltage bias generator further comprises a feedback path to receive a feedback signal to alter the first current based on a value of the feedback signal and the second current is generated by a constant current source during operation of the electronic data storage system;

the load comprises a plurality of sense amplifiers coupled to the voltage bias generator; and

the voltage bias generator further comprises a sense amplifier model circuit to generate a current component of the first current, wherein components of the sense amplifier model circuit track one or more changes in electrical properties of the sense amplifiers due to environmental changes; and

a plurality of memory cells coupled to the sense amplifiers.

27. An electronic data storage system comprising:

a voltage bias generator to generate a voltage bias for a load from a comparison between a first current and a second current, wherein:

the voltage bias generator further comprises a feedback path to receive a feedback signal to alter the first current based on a value of the feedback signal and the second current is generated by a constant current source during operation of the electronic data storage system;

the load comprises sense amplifier components; and

the voltage bias generator further comprises a current differential amplifier to compare the first current to the second current and to generate a difference current, wherein the difference current comprises a reference current minus a sense amplifier reference current, wherein during operation of the electronic data storage system the sense amplifier reference current varies in accordance with changes in components that model the sense amplifier components of the load.

Assignments (24)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2025
From: NXP USA, INC.
To: ASCALE TECHNOLOGIES LLC
Reel/Frame 070026/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024079/0082 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2006
From: CHOY, JON S.; WANG, YANZHUO
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018019/0139 →