Direct digital synthesis circuit
View Patent ↗A direct digital synthesis circuit ( 108 ) includes a plurality of current sources ( 210, 211, 212 ), an output circuit ( 200 ), and a logical multiplier circuit ( 202 ). The output circuit ( 200 ) provides a synthesized waveform ( 164 ) output and includes a first ( 206 ) and second branch ( 208 ). The logical multiplier circuit ( 202 ) is operatively coupled to the plurality of current sources ( 210, 211, 212 ) and to the output circuit ( 200 ). The logical multiplier circuit ( 202 ) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch ( 206 ) by a determined magnitude and decrease a second current flow through the second branch ( 208 ) by the determined magnitude based on the plurality of signals. The synthesized waveform ( 164 ) is based on the first and second currents.
1. A direct digital synthesis circuit comprising:
a plurality of current sources;
an output circuit, comprising a first and second branch, that provides a synthesized waveform output; and
a logical multiplier circuit, operatively coupled to the plurality of current sources and to the output circuit, that is operative to receive a plurality of signals and selectively increase a first current flow through the first branch by a determined magnitude and decrease a second current flow through the second branch by the determined magnitude based on the plurality of signals, wherein the synthesized waveform is based on the first and second currents.
2. The direct digital synthesis circuit of claim 1 wherein the first branch comprises a first resistive element operatively coupled to the logical multiplier circuit and the second branch comprises a second resistive element operatively coupled to the logical multiplier circuit.
3. The direct digital synthesis circuit of claim 1 wherein the output circuit further comprises a resistive element operatively coupled between the first and second branches and wherein the first branch comprises a first current source operatively coupled to the logical multiplier circuit and to the resistive element and the second branch comprises a second current source operatively coupled to the logical multiplier circuit and to the resistive element.
4. The direct digital synthesis circuit of claim 1 wherein the plurality of current sources are operative to receive a modulating signal and wherein the determined magnitude of current flow is based on the modulating signal.
5. The direct digital synthesis circuit of claim 1 wherein the logical multiplier circuit comprises N logical multiplication cells that each comprise a plurality of metal oxide semiconductor field effect transistor (MOSFET) logical multiplication stages, wherein N is greater than 1, and wherein the N logical multiplication cells provide suppression of up to a 4N-2 harmonic in the synthesized waveform output.
6. The direct digital synthesis circuit of claim 5 wherein each of the plurality of MOSFET logical multiplication stages comprise a first, second, and third MOSFET, wherein the first MOSFET includes a first terminal operatively coupled to the output circuit, the second MOSFET includes a second terminal operatively coupled to the output circuit, and the third MOSFET includes a third terminal operatively coupled to at least one of the plurality of current sources and a fourth terminal operatively coupled to a fifth terminal of the first MOSFET and to a sixth terminal of the second MOSFET.
7. An integrated circuit comprising:
a subcarrier oscillator circuit that is operative to generate a subcarrier frequency;
a control signal generator that is operative to receive the subcarrier frequency and generate a plurality of signals based thereon; and
a direct digital synthesis circuit that comprises:
a plurality of current sources,
an output circuit, comprising a first and second branch, that provides a synthesized waveform output, and
a logical multiplier circuit, operatively coupled to the plurality of current sources and to the output circuit, that is operative to receive the plurality of signals and selectively increase a first current flow through the first branch by a determined magnitude and decrease a second current flow through the second branch by the determined magnitude based on the plurality of signals, wherein the synthesized waveform is based on the first and second currents.
8. The integrated circuit of claim 7 wherein the first branch comprises a first resistive element operatively coupled to the logical multiplier circuit and the second branch comprises a second resistive element operatively coupled to the logical multiplier circuit.
9. The integrated circuit of claim 7 wherein the output circuit further comprises a resistive element operatively coupled between the first and second branches and wherein the first branch comprises a first current source operatively coupled to the logical multiplier circuit and to the resistive element and the second branch comprises a second current source operatively coupled to the logical multiplier circuit and to the resistive element.
10. The integrated circuit of claim 7 wherein the plurality of current sources are operative to receive an amplitude modulating signal and wherein the determined magnitude of current flow is based on the amplitude modulating signal.
11. The integrated circuit of claim 7 wherein the logical multiplier circuit comprises N logical multiplication cells that each comprise a plurality of metal oxide semiconductor field effect transistor (MOSFET) logical multiplication stages, wherein N is greater than 1, and wherein the N logical multiplication cells provide suppression of up to a 4N-2 harmonic in the synthesized waveform output.
12. The integrated circuit of claim 11 wherein each of the plurality of MOSFET logical multiplication stages comprise a first, second, and third MOSFET, wherein the first MOSFET includes a first terminal operatively coupled to the output circuit, the second MOSFET includes a second terminal operatively coupled to the output circuit, and the third MOSFET includes a third terminal operatively coupled to at least one of the plurality of current sources and a fourth terminal operatively coupled to a fifth terminal of the first MOSFET and to a sixth terminal of the second MOSFET.
13. The integrated circuit of claim 7 further comprising a radio frequency mixer operative to generate a radio frequency signal based on the synthesized waveform.
14. The integrated circuit of claim 7 wherein the subcarrier oscillator is operative to receive a frequency modulating signal and generate the subcarrier frequency based thereon.
15. An apparatus comprising:
an input circuit operative to generate a baseband signal; and
a modulation circuit that comprises:
a baseband circuit operative to receive the baseband signal and generate a modulating signal based thereon,
a subcarrier oscillator circuit that is operative to generate a subcarrier frequency, and
a control signal generator that is operative to receive the subcarrier frequency and generate a plurality of signals based thereon, and
a direct digital synthesis circuit that comprises:
a plurality of current sources,
an output circuit, comprising a first and second branch, that provides a synthesized waveform output, and
a logical multiplier circuit, operatively coupled to the plurality of current sources and to the output circuit, that is operative to receive the plurality of signals and selectively increase a first current flow through the first branch by a determined magnitude and decrease a second current flow through the second branch by the determined magnitude based on the plurality of signals, wherein the determined magnitude is based on the modulating signal and the synthesized waveform is based on the first and second currents.
16. The apparatus of claim 15 wherein the first branch comprises a first resistive element operatively coupled to the logical multiplier circuit and the second branch comprises a second resistive element operatively coupled to the logical multiplier circuit.
17. The apparatus of claim 15 wherein the output circuit further comprises a resistive element operatively coupled between the first and second branches and wherein the first branch comprises a first current source operatively coupled to the logical multiplier circuit and to the resistive element and the second branch comprises a second current source operatively coupled to the logical multiplier circuit and to the resistive element.
18. The apparatus of claim 15 wherein the logical multiplier circuit comprises a plurality of logical multiplication cells that each comprise a plurality of metal oxide semiconductor field effect transistor (MOSFET) logical multiplication stages.
19. The apparatus of claim 18 wherein each of the plurality of MOSFET logical multiplication stages comprise a first, second, and third MOSFET, wherein the first MOSFET includes a first terminal operatively coupled to the output circuit, the second MOSFET includes a second terminal operatively coupled to the output circuit, and the third MOSFET includes a third terminal operatively coupled to at least one of the plurality of current sources and a fourth terminal operatively coupled to a fifth terminal of the first MOSFET and to a sixth terminal of the second MOSFET.
20. The apparatus of claim 15 comprising a mixer operatively coupled to the direct digital synthesis circuit and operative to produce a modulated signal based on the synthesized waveform output.