Semiconductor component and method of manufacturing
View Patent ↗A semiconductor component includes a substrate ( 110 ) having a surface, a channel region ( 120, 220 ) located in the substrate, a non-electrically conductive region ( 130 ) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region ( 140, 240 ) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region ( 150, 350, 450, 550 ) located in the substrate and contiguous with the non-electrically conductive region.
1. A method of manufacturing a semiconductor component comprising:
providing a substrate having a surface;
forming by a non LOCal Oxidation of Silicon (LOCOS) process, a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the substrate;
forming a drift region in the substrate;
forming a channel region in the substrate, at least a portion of the drift region located between the channel region and the non-electrically conductive region; and
forming an electrically floating region in the substrate and contiguous with the non-eletrically conductive region;
wherein at least a portion of the electrically floating region is located between the non-electrically conductive region and the channel region, at least a portion of the electrically floating region is located laterally with respect to the non-electrically conductive region, and at least a portion of the electrically floating region is located underneath the non-electrically conductive region.
2. The method of claim 1 wherein forming the channel region and forming the electrically floating region occur simultaneously with each other.
3. The method of claim 1 wherein the forming by a non LOCal Oxidation of Silicon (LOCOS) process, the non-electrically conductive region further comprises:
etching a trench into the surface of the substrate; and
filling the trench with a material.
4. The method of claim 3 wherein the material includes a semi insulative material.
5. The method of claim 3 wherein the material includes a dielectric material.
6. The method of claim 3 wherein the material includes at least one of silicon dioxide, silicon nitride, and gallium arsenide.
7. The method of claim 3 further comprising:
forming a thermal liner oxide layer along walls of the trench prior to the filling.
8. The method of claim 3 further comprising:
densifying the material.
9. The method of claim 3 further comprising:
planarizing the material.
10. The method of claim 1 wherein the forming by a non LOCal Oxidation of Silicon (LOGCS) process, the non-electrically conductive region further includes implanting a dose of oxygen into the surface at a substrate at location corresponding to non-electrically conductive region.
11. A method of manufacturing a semiconductor component comprising:
providing a substrate having a surface;
forming by a non LOCal Oxidation of Silicon (LOCOS) process, a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the substrate;
forming a drift region in the substrate;
forming a channel region in the substrate, at least a portion of the drift region located between the channel region and the non-electrically conductive region; and
forming an electrically floating region in the substrate and contiguous with the non-electrically conductive region;
wherein at least a portion of the channel region, at least a portion of the non-electrically conductive region, at least a portion of the drift region, and at least a portion of the electrically floating region are located at the surface of the substrate.
12. The method of claim 1 wherein at least a portion of the electrically floating region is located between the drift region and the non-electrically conductive region.
13. The method of claim 12 wherein at least a portion of the channel region, at least a portion of the non-electrically conductive region, at least a portion of the drift region, and at least a portion of the electrically floating region are located at the surface of the substrate.
14. The method of claim 13 wherein a portion of the electrically floating region at the surface of the substrate is located between a portion of the drift region at the surface of the substrate and a portion of the non-electrically conductive region at the surface of the substrate.
15. A method of manufacturing a semiconductor component comprising:
providing a substrate having a surface;
forming by a non LOCal Oxidation of Silicon (LOCOS) process, a non-electrically conductive region substantially located below a substantially planar plane, defined by the surface of the substrate;
forming a drift region in the substrate;
forming a channel region in the substrate, at least a portion of the drift region located between the channel region and the non-electrically conductive region; and
forming an electrically floating region in the substrate and contiguous with the non-electrically conductive region;
forming a drain region in the substrate;
wherein:
the non-electrically conductive region is located between the drain region and the channel region; and
at least a portion of the electrically floating region at the surface of the substrate is located between the non-electrically conductive region and the drain region.
16. The method of claim 15 wherein at least a portion of the channel region, at least a portion of the non-electrically conductive region, at least a portion of the drift region, and at least a portion of the electrically floating region are located at the surface of the substrate.
17. The method of claim 1 wherein at least a portion of the channel region, at least a portion of the non-electrically conductive region, at least a portion of the drift region, and at least a portion of the electrically floating region are located at the surface of the substrate.
18. The method of claim 1 wherein the channel region is electrically isolated from a portion of the substrate located underneath the channel region.
19. A method of manufacturing a semiconductor component comprising:
providing a substrate having a surface;
forming by a non LOCal Oxidation of Silicon (LOCOS) process, a non-electrically conductive region substantially located below a substantially planar plane defined by the surface of the substrate;
forming a drift region in the substrate;
forming a channel region in the substrate, at least a portion of the drift region located between the channel region and the non-electrically conductive region; and
forming an electrically floating region in the substrate and contiguous with the non-electrically conductive region;
wherein the channel region is electrically coupled to a portion of the substrate located underneath the channel region;
wherein at least a portion of the channel region, at least a portion of the non-electrically conductive region, at least a portion of the drift region, and at least a protion of the electrically floating region are located at the surface of the substrate.
20. The method of claim 19 wherein the electrically floating region is located between the drift region and the non-electrically conductive region.
21. The method of claim 19 wherein at least a portion of the electrically floating region is located underneath the non-electrically conductive region.
22. The method of claim 19 wherein the electrically floating region is located only underneath the non-electrically conductive region.
23. The method of claim 19 wherein at least a portion of the electrically floating region is located between the non-electrically conductive region and the channel region and at least a portion of the electrically floating region is located underneath the non-electrically conductive region.
24. The method of claim 1 further comprising:
forming a gate electrode over the surface of the substrate,
wherein:
the channel region is located under the gate electrode;
the drift region is located at least partially under the gate electrode; and
the electrically floating region is located at least partially under the gate electrode.
25. The method of claim 24 wherein:
the electrically floating region has a doping type;
the drift region has an other doping type different from the doping type of the electrically floating region and is located under the electrically floating region, and
a portion of the substrate has the doping type of the electrically floating region and is located under the drift region and under the electrically floating region.
26. The method of claim 25 wherein the electrically floating region is located under the non-electrically conductive region.
27. The method of claim 25 wherein the non-electrically conductive region is located under the gate electrode.
28. The method of claim 1 wherein:
the electrically floating region has a doping type;
the drift region has an other doping type different from the doping type of the electrically floating region and is located at least partially under the electrically floating region, and
a portion of the substrate has the doping type of the electrically floating region and is located at least partially under the drift region and located at least partially under the electrically floating region.
29. The method of claim 11 wherein:
the electrically floating region comprises a first portion and a second portion;
the first portion of the electrically floating region is located at least partially underneath the non-electrically conductive region; and
the second portion of the electrically floating region includes a portion that is located at the surface of the substrate between a portion of the drift region at the surface of the substrate and a portion of the non-electrically conductive region at the surface of the substrate.
30. The method of claim 29 wherein the first portion of the electrically floating region is separate from the second portion of the electrically floating region.
31. The method of claim 1 further comprising:
forming a gate dielectric over at least a portion of the non-electrically conductive region.
32. The method of claim 1 wherein at least a portion of the electrically floating region is located laterally between the non-electrically conductive region and the channel region.