Semiconductor fabrication process for modifying the profiles of patterned features
View Patent ↗A method for forming a sacrificial layer ( 30 ) over patterned structures ( 28 ) to allow structures ( 28 ) to be trimmed laterally without incurring much loss vertically. Structures ( 28 ) are patterned on a first layer ( 26 ) of a substrate ( 24 ). Thereafter, sacrificial layer ( 30 ) is deposited on structures ( 28 ). During this deposition, the thickness of sacrificial layer ( 28 ) grows vertically above structures ( 28 ) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer ( 30 ) and patterned structures ( 28 ) are then etched where the etch rate uniformity ensures that the sacrificial layer ( 30 ) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.
1. A method for forming an integrated circuit on a semiconductor wafer, comprising:
forming a patterned structure having horizontal surfaces and vertical surfaces over a first layer of a substrate of the wafer;
depositing a polymer layer on the patterned structure wherein the thickness of the polymer layer on the horizontal surfaces is substantially uniform and greater than its substantially uniform thickness on the vertical surfaces; and
etching the polymer layer and patterned structure with an etch uniformity sufficient to remove vertical portions of the polymer layer and etch vertical surfaces of the patterned structure before etching horizontal surfaces of the patterned structure.
2. The method of claim 1 , wherein said forming of the polymer layer and said etching of the polymer layer and patterned structure are performed concurrently using a plasma comprising fluorocarbon and oxygen gases.
3. The method of claim 1 , wherein said the width of the patterned structure is reduced by the etching of the polymer layer and the patterned structure while the height of the patterned structure is substantially undiminished.
4. The method of claim 1 , further comprising etching away regions of the first layer remaining exposed by the patterned structure subsequent to etching the polymer layer and the patterned structure.
5. The method of claim 1 , wherein the patterned structure is a photoresist structure or a hard mask structure comprising silicon nitride.
6. A method for forming an integrated circuit on a semiconductor wafer, comprising:
forming a patterned structure having horizontal surfaces and vertical surfaces over a first layer of a substrate of the wafer;
non-uniformly depositing a polymer layer on the patterned structure wherein the thickness of the polymer layer on the horizontal surfaces is greater than its thickness on the vertical surfaces;
etching the polymer layer and patterned structure with an etch uniformity sufficient to remove vertical portions of the polymer layer and etch vertical surfaces of the patterned structure before etching horizontal surfaces of the patterned structure; and
repeating said forming of the polymer layer and said etching of the polymer layer and patterned structure one or more times, wherein each iteration removes an incremental portion of the patterned structure vertical surfaces.
7. A method for forming an integrated circuit on a semiconductor wafer, comprising:
forming a patterned structure having horizontal surfaces and vertical surfaces over a first layer of a substrate of the wafer;
non-uniformly depositing a polymer layer on the patterned structure wherein the thickness of the polymer layer on the horizontal surfaces is greater than its thickness on the vertical surfaces; and
etching the polymer layer and patterned structure with an etch uniformity sufficient to remove vertical portions of the polymer layer and etch vertical surfaces of the patterned structure before etching horizontal surfaces of the patterned structure;
wherein said forming of the polymer layer comprises forming a fluorocarbon polymer by exposing the wafer to a fluorocarbon-containing plasma; and
wherein ions in the plasma have an energy of less than about 70 eV.
8. The method of claim 7 , wherein ions in the plasma have an energy of less than about 30 eV.
9. The method of claim 7 , wherein the etching of the polymer layer and the patterned structure comprises exposing the wafer to an oxygen-containing plasma.
10. The method of claim 7 , wherein the etching of the polymer layer and the patterned structure comprises exposing the wafer to a plasma comprising O 2 , HBr, and Ar.
11. A method of forming an integrated circuit on a semiconductor wafer, comprising:
forming a patterned structure having horizontal surfaces and vertical surfaces over a first layer of the wafer;
depositing a sacrificial layer over the patterned structure wherein a portion of the sacrificial layer overlying the patterned structure's vertical services has a uniform first thickness and wherein the portion of the sacrificial layer adjacent the patterned structures horizontal surfaces has substantially uniform second thickness, wherein the first thickness is less than the second thickness;
removing portions of the sacrificial layer over the patterned structure's vertical surfaces to expose the vertical surfaces while retaining at least some of the sacrificial layer over horizontal portions of the patterned structure; and
etching the exposed vertical surfaces of the patterned structures to reduce the lateral width of the structures without substantially reducing the vertical height of the structures.
12. The method of claim 11 , wherein the patterned structure comprises photoresist and wherein depositing the sacrificial layer comprises forming a polymer layer over the patterned structure.
13. The method of claim 12 , wherein forming the polymer layer comprises exposing the wafer to a fluorocarbon plasma at an energy of less than approximately 30 eV.
14. The method of claim 13 , wherein removing portion of the sacrificial layer comprises exposing the wafer to an oxygen plasma.
15. The method of claim 11 , wherein depositing the sacrificial layer comprises depositing the sacrificial preferentially on the patterned structure horizontal surfaces wherein a thickness of the sacrificial layer over the patterned structure horizontal surfaces is greater than a thickness of the sacrificial layer over the patterned structure vertical surfaces.
16. The method of claim 15 , wherein removing portions of the sacrificial layer comprises etching the sacrificial layer wherein the etch rate uniformity is sufficient to clear portions of the sacrificial layer over the vertical surfaces before clearing sacrificial layer portions of the horizontal surfaces.