Non-volatile memory device and method for forming
View Patent ↗A semiconductor device ( 10 ) has a highly doped layer ( 26 ) having a first conductivity type uniformly implanted into the semiconductor substrate ( 20 ). An oxide-nitride-oxide structure ( 36, 38, 40 ) is formed over the semiconductor substrate ( 20 ). A halo region ( 46 ) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source ( 52 ) and drain ( 54 ) having a second conductivity type are implanted into the substrate ( 20 ). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region ( 46 ) on the drain side allows a higher programming speed, and the highly doped layer ( 26 ) allows the use of a short channel device.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first highly doped layer having a first conductivity type formed in the semiconductor substrate a first distance below a surface of the semiconductor substrate;
a first insulating layer formed over the semiconductor substrate;
a charge storage layer formed over the first insulating layer;
a second insulating layer formed over the charge storage layer;
a source having a second conductivity type formed in a first predetermined region of the semiconductor substrate;
a drain having the second conductivity type formed in a second predetermined region of the semiconductor substrate, wherein the first highly doped layer does not extend below a depth of the source and the drain;
a channel region between the source and the drain below the first insulating layer; and
a second highly doped layer having the first conductivity type formed in only a drain side of the first insulating layer and extending through the drain and under the first insulating layer a second distance from an edge of the first insulating layer, wherein the second highly doped region increases a dopant gradient within the second distance;
wherein the semiconductor device is a non-volatile memory cell and during an access to the non-volatile memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second distance.
2. The semiconductor device of claim 1 , wherein the semiconductor substrate directly below the first insulating layer and above the first highly doped layer has a dopant concentration lower than a dopant concentration of the first highly doped layer.
3. The semiconductor device of claim 2 , wherein the semiconductor substrate directly below the first insulating layer is the first conductivity type.
4. The semiconductor device of claim 2 , wherein the charge storage layer comprises nitride.
5. The semiconductor device of claim 2 , wherein the semiconductor substrate directly below the first insulating layer is the second conductivity type, different from the first conductivity type.
6. The semiconductor device of claim 1 , wherein the charge storage layer comprises polysilicon.
7. The semiconductor device of claim 1 , wherein the charge storage layer comprises a plurality of nanocrystals.
8. The semiconductor device of claim 1 , wherein the first highly doped layer or the second highly doped layer is implanted using indium.
9. The semiconductor device of claim 1 , wherein the channel region formed between the source and the drain below the first insulating layer has a length of between 0.35 micron and 0.06 micron.
10. The semiconductor device of claim 1 , wherein the second highly doped region is implanted at an angle determined to increase the dopant gradient within the second distance and to maintain a relatively low dopant concentration within the channel region.
11. A method for forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming a first highly doped layer having a first conductivity type into the semiconductor substrate a first distance below a surface of the semiconductor substrate;
forming a first insulating layer over the semiconductor substrate;
forming a charge storage layer over the first insulating layer;
forming a second insulating layer over the charge storage layer;
forming a source having a second conductivity type into a first predetermined region of the semiconductor substrate;
forming a drain having the second conductivity type into a second predetermined region of the semiconductor substrate, wherein the first highly doped layer does not extend below a depth of the source and the drain; and
forming a second highly doped layer having the first conductivity type in only a drain side of the first insulating layer and extending through the drain and under the first insulating layer a second distance from an edge of the first insulating layer, wherein the second highly doped region increases a dopant gradient within the second distance;
wherein a channel region is formed between the source and the drain below the first insulating layer, and wherein the semiconductor device is a non-volatile memory cell and during an access to the non-volatile memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second distance.
12. The method of claim 11 , wherein the semiconductor substrate directly below the first insulating layer and above the first highly doped layer has a dopant concentration lower than a dopant concentration of the first highly doped layer.
13. The method of claim 11 , further comprising forming a gate electrode over the second insulating layer.
14. The method of claim 13 , further comprising forming a masking layer over the source and the gate electrode before implanting the second highly doped layer.
15. The method of claim 11 , wherein the charge storage layer comprises nitride.
16. The method of claim 11 , wherein the charge storage layer comprises polysilicon.
17. The method of claim 11 , wherein the charge storage layer comprises a plurality of nanocrystals.
18. The method of claim 11 , wherein the first highly doped layer and/or the second highly doped layer is implanted using indium.
19. The method of claim 11 , wherein the channel region formed between the source and the drain below the first insulating layer has a length of between 0.35 micron and 006 micron.
20. The method of claim 11 , wherein the second highly doped region is implanted at an angle determined to increase the dopant gradient within the second distance and to maintain a relatively low dopant concentration within the channel region.
21. A semiconductor device, comprising:
a semiconductor substrate;
a highly doped layer having a first conductivity type formed in the semiconductor substrate a first distance below a surface of the semiconductor substrate;
an oxide-nitride-oxide structure formed over the semiconductor substrate;
a gate electrode formed over the oxide-nitride-oxide structure;
a source having a second conductivity type formed in a first predetermined region of the semiconductor substrate;
a drain having the second conductivity type formed in a second predetermined region of the semiconductor substrate, wherein the first highly doped layer does not extend below a depth of the source and the drain;
a channel region between the source and the drain below the first insulating layer; and
an angled halo having the first conductivity type formed in only a drain side of the oxide-nitride-oxide structure and extending through the drain and under the oxide-nitride-oxide structure a second distance from an edge of the oxide-nitride-oxide structure, wherein the angled halo increases a dopant gradient within the second distance,
wherein the semiconductor device is a non-volatile memory cell and during an access to the non-volatile memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second distance.
22. The semiconductor device of claim 21 , wherein the semiconductor substrate directly below the oxide-nitride-oxide structure and above the highly doped layer has a dopant concentration lower than a dopant concentration of the highly doped layer.
23. The semiconductor device of claim 22 , wherein the semiconductor substrate directly below the oxide-nitride-oxide structure is the first conductivity type.
24. The semiconductor device of claim 22 , wherein the semiconductor substrate directly below the oxide-nitride-oxide structure is of a second conductivity type, different from the first conductivity type.
25. The semiconductor device of claim 21 , wherein the highly doped layer and/or the angled halo is implanted using indium.
26. The semiconductor device of claim 21 , wherein the angled halo is implanted at an angle determined to increase the dopant gradient within the second distance and to maintain a relatively low dopant concentration within a channel region formed between the source and the drain below the oxide-nitride-oxide structure.
27. The semiconductor device of claim 1 , wherein the first highly doped layer is uniformly implanted into the semiconductor substrate the first distance below the surface of the semiconductor substrate.
28. The semiconductor device of claim 21 , wherein the first highly doped layer is uniformly implanted into the semiconductor substrate the first distance below the surface of the semiconductor substrate.
29. A semiconductor device, comprising:
a semiconductor substrate;
a first highly doped p-type layer formed in the semiconductor substrate at a first distance below a surface of the semiconductor substrate, wherein the first highly doped layer is formed using indium as a dopant;
a first insulating layer formed over the semiconductor substrate;
a charge storage layer formed over the first insulating layer;
a second insulating layer formed over the charge storage layer;
an n-type source formed in a first predetermined region of the semiconductor substrate;
an n-type drain formed in a second predetermined region of the semiconductor substrate, wherein the first highly doped p-type layer does not extend below a depth of the n-type source and the n-type drain;
a channel region between the n-type source and the n-type drain below the first insulating layer; and
a second highly doped p-type layer formed in only a drain side of the first insulating layer and extending through the n-type drain and under the first insulating layer a second distance from an edge of the first insulating layer, wherein the second highly doped p-type layer is formed using indium as a dopant.