Clock tree adjustable buffer
View Patent ↗An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the first output node. A clock distribution system including multiple uniform adjustable buffers coupled between at least one root node and multiple destination nodes, where each uniform adjustable buffer is adjustable between a minimum delay and a maximum delay.
1. A clock distribution system, comprising:
a plurality of uniform adjustable buffers coupled between at least one root node and a plurality of destination nodes, wherein each of said plurality of uniform adjustable buffers is adjustable between a minimum delay and a maximum delay,
wherein at least one of said plurality of uniform adjustable buffers comprises:
a first plurality of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node and having a corresponding first plurality of control electrodes, wherein each of said first plurality of control electrodes is coupled to a selected one of an input node and a second voltage supply collectively forming a first plurality of selectable connections; and
a first plurality of N-channel devices having current paths coupled in series between said first output node and said second voltage supply and having a corresponding second plurality of control electrodes, wherein each of said second plurality of control electrodes is coupled to a selected one of said input node and said first voltage supply collectively forming a second plurality of selectable connections;
wherein said first and second plurality of selectable connections are made to adjust delay from said input node to said first output node;
a first branch comprising a first set of said plurality of uniform adjustable buffers coupled in series between said at least one root node and a first destination node; and
a second branch comprising a second set of said plurality of uniform adjustable buffers coupled in series between said at least one root node and a second destination node;
wherein each of said plurality of uniform adjustable buffers of said first set is programmed with said minimum delay and wherein at least one of said plurality of uniform adjustable buffers of said second set is programmed with a larger delay than said minimum delay.
2. The clock distribution system of claim 1 , wherein said plurality of uniform adjustable buffers are initially routed assuming each has said minimum delay and wherein at least one of said plurality of uniform adjustable buffers of said second set is adjusted to minimize delay differential between said first and second branches.
3. The clock distribution system of claim 1 , wherein said first and second branches are part of a first clock tree routed from a first root node, further comprising a second clock tree including a third branch comprising a third set of said plurality of uniform adjustable buffers coupled in series between a second root node and a third destination node.
4. The clock distribution system of claim 3 , further comprising:
said plurality of uniform adjustable buffers initially being routed assuming that each has said minimum delay;
said first clock tree initially having a first delay and said second clock tree initially having a second delay that is less than said first delay; and
at least one additional uniform adjustable buffer coupled to said third root node to increase delay of said second clock tree.
5. The clock distribution system of claim 1 , wherein each of said plurality of uniform adjustable buffers comprises an inverting buffer.
6. The clock distribution system of claim 1 , wherein said first plurality of P-channel devices comprises a first number of P-channel devices and wherein said first plurality of N-channel devices comprises a second number of N-channel devices wherein said first and second numbers are equal.
7. The clock distribution system of claim 1 , wherein said first plurality of P-channel devices comprises a first number of P-channel devices and wherein said first plurality of N-channel devices comprises a second number of N-channel devices wherein said first and second numbers are different.
8. The clock distribution system of claim 1 , wherein said first and second plurality of selectable connections are imbalanced to compensate delay differences between rising and falling edge transitions.
9. The clock distribution system of claim 1 , wherein said first plurality of P-channel devices comprises first and second P-channel devices and wherein said second plurality of N-channel devices comprises first and second N-channel devices.
10. The clock distribution system of claim 1 , wherein said control electrode of said first P-channel device is coupled to said second voltage supply, said control electrode of said second N-channel device is coupled to said first voltage supply, and said control electrodes of said second P-channel device and said first N-channel device are coupled to said input node for a relatively small delay configuration, wherein said control electrode of said second P-channel device is coupled to said second voltage supply, said control electrode of said first N-channel device is coupled to said first voltage supply, and said control electrodes of said first P-channel device and said second N-channel device are coupled to said input node for a medium delay configuration, and wherein said control electrodes of said first and second P-channel and N-channel devices are coupled to said input node for a relatively large delay configuration.
11. The clock distribution system of claim 1 , further comprising:
a second plurality of P-channel devices having current electrodes coupled in series between said first voltage supply and a second output node and having a corresponding third plurality of control electrodes, wherein each of said third plurality of control electrodes is coupled to a selected one of said first output node and said second voltage supply collectively forming a third plurality of selectable connections; and
a second plurality of N-channel devices having current paths coupled in series between said second output node and said second voltage supply and having a corresponding fourth plurality of control electrodes, wherein each of said fourth plurality of control electrodes is coupled to a selected one of said first output node and said first voltage supply collectively forming a fourth plurality of selectable connections;
wherein said third and fourth plurality of selectable connections are made to adjust delay from said first output node to said second output node.
12. The clock distribution system of claim 1 , wherein said first, second, third and fourth plurality of selectable connections are imbalanced to compensate delay differences between rising and falling edge transitions.
13. A method of distributing a clock signal for a circuit, comprising:
distributing a first plurality of adjustable buffers from a first root node to a plurality of first destination nodes forming a plurality of first branches of a first clock tree, wherein at least one of said plurality of first branches comprises at least two of said first plurality of adjustable buffers coupled in series,
wherein at least one of said plurality of uniform adjustable buffers comprises:
a first plurality of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node and having a corresponding first plurality of control electrodes, wherein each of said first plurality of control electrodes is coupled to a selected one of an input node and a second voltage supply collectively forming a first plurality of selectable connections; and
a first plurality of N-channel devices having current paths coupled in series between said first output node and said second voltage supply and having a corresponding second plurality of control electrodes, wherein each of said second plurality of control electrodes is coupled to a selected one of said input node and said first voltage supply collectively forming a second plurality of selectable connections;
wherein said first and second plurality of selectable connections are made to adjust delay from said input node to said first output node;
determining a delay of each of the plurality of first branches assuming a predetermined minimum delay for each adjustable buffer and determining a slowest branch of the first clock tree; and
adjusting at least one adjustable buffer of each of the plurality of first branches other than the slowest branch to minimize delay differential between the plurality of first branches.
14. The method of claim 13 , wherein said distributing a first plurality of adjustable buffers comprises distributing inverting buffers.
15. The method of claim 13 , wherein said adjusting at least one adjustable buffer comprises selectively coupling control electrodes of each of a plurality of pull-up devices and each of a plurality of pull-down devices between voltage supplies and buffer inputs to adjust timing.
16. The method of claim 13 , further comprising adjusting selected ones of the first plurality of adjustable buffers to add imbalance to compensate for timing discrepancies between rising and falling edge transitions.
17. The method of claim 13 , further comprising:
distributing a second plurality of adjustable buffers from a second root node to at least one second destination node forming at least one second branch of a second clock tree;
determining a delay of each second branch assuming the predetermined minimum delay for each adjustable buffer and determining a slowest branch of the first and second clock trees; and
adjusting at least one adjustable buffer of each of the plurality of first and second branches other than the slowest branch to minimize delay differential between the plurality of first and second branches.
18. The method of claim 17 , further comprising inserting at least one additional buffer to a faster one of the first and second clock trees.
19. The method of claim 17 , further comprising inserting at least one additional buffer to a faster one of the first and second clock trees if a delay differential between said first and second clock trees is greater than the predetermined minimum delay for each adjustable buffer.