Silicon deposition over dual surface orientation substrates to promote uniform polishing
View Patent ↗A semiconductor process and apparatus provide a planarized hybrid substrate ( 16 ) by selectively depositing an epitaxial silicon layer ( 70 ) to fill a trench ( 96 ), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon ( 102 ) over the epi silicon layer ( 70 ) and polycrystalline silicon ( 101, 103 ) over the nitride mask layer ( 95 ). The polysilicon material ( 101, 103 ) added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface ( 100 ) over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes ( 151 ) over a first SOI layer ( 90 ) using deposited ( 100 ) silicon and forming second gate electrodes ( 161 ) over an epitaxially grown ( 110 ) silicon layer ( 70 ), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes ( 161 ) having improved hole mobility.
1. A method for fabricating a dual surface orientation semiconductor structure, comprising:
forming a first semiconductor layer having a first crystal orientation;
forming a second semiconductor layer over at least part of the first semiconductor layer, wherein the second semiconductor layer is electrically isolated from the first semiconductor layer and has a second crystal orientation that is different from the first crystal orientation;
forming a mask over the second semiconductor layer;
using the mask to form a trench opening that exposes the first semiconductor layer without exposing the second semiconductor layer;
filling at least part of a trench opening by epitaxially growing a first epitaxial semiconductor material on at least an exposed surface of the first semiconductor layer to form a first epitaxial semiconductor layer that is electrically isolated from the second semiconductor layer; and
blanket depositing silicon to form a polysilicon layer on the mask and to form a crystalline silicon layer to thicken the first epitaxial semiconductor layer so that the polysilicon layer and crystalline silicon layer are substantially coplanar.
2. The method of claim 1 , further comprising performing a chemical mechanical polish step to remove the polysilicon layer and at least part of the crystalline silicon layer so that the first epitaxial semiconductor layer is substantially coplanar across feature sizes.
3. The method of claim 1 , wherein the mask is formed from a nitride layer.
4. The method of claim 1 , wherein the second semiconductor layer comprises (100) p-type silicon and the first epitaxial semiconductor layer comprises (110) n-type silicon.
5. The method of claim 1 , wherein the second semiconductor layer comprises (100) p-type silicon and the first epitaxial semiconductor layer comprises (110) n-type silicon that is epitaxially grown from an exposed surface of the first semiconductor layer.
6. The method of claim 1 , where epitaxially growing silicon on an exposed surface of the first semiconductor layer comprises a selective silicon deposition step that completely fills the trench.
7. The method of claim 1 , further comprising forming the second semiconductor layer over a buried oxide layer to form a semiconductor-on-insulator substrate.
8. The method of claim 1 , where the second semiconductor layer is electrically isolated from the first epitaxial semiconductor layer by a shallow trench isolation region.
9. The method of claim 1 , further comprising:
forming a first gate electrode structure over the first epitaxial semiconductor layer, said first gate electrode structure comprising at least a first relatively high-k dielectric gate layer and a first conductive layer; and
forming a second gate electrode structure over the second semiconductor layer, said second gate electrode structure comprising at least a second relatively high-k dielectric gate layer and a second conductive layer.
10. The method of claim 1 , further comprising performing a chemical mechanical polish step and a chemical etch to completely remove the polysilicon layer so that the second semiconductor layer and the first epitaxial semiconductor layer are substantially coplanar.
11. A method for forming a semiconductor structure on a wafer, comprising:
forming a first semiconductor layer having a first crystal orientation;
forming a second semiconductor layer and an adjacent isolation region over at least part of the first semiconductor layer, wherein the second semiconductor layer is electrically isolated from the first semiconductor layer and has a second crystal orientation that is different from the first crystal orientation;
filling at least part of a trench opening that exposes the first semiconductor layer without exposing the second semiconductor layer by epitaxially growing a first epitaxial semiconductor layer on at least an exposed surface of the first semiconductor layer;
non-selectively depositing silicon to cover the wafer with a near uniform thickness of silicon comprising polysilicon and crystalline silicon, where the crystalline silicon thickens the first epitaxial semiconductor layer and the second semiconductor layer; and
performing a chemical mechanical polish step to remove the polysilicon and at least part of the second semiconductor layer and first epitaxial semiconductor layer so that the second semiconductor layer is substantially coplanar with the first epitaxial semiconductor layer.
12. The method of claim 11 , where filling at least part of a trench opening comprises:
forming a mask layer over at least the second semiconductor layer and a portion of the isolation region;
patterning and etching the mask layer to form an opening through the isolation region and to the first semiconductor layer; and
epitaxially growing the first epitaxial semiconductor layer on at least an exposed surface of the first semiconductor layer to form a first epitaxial semiconductor layer that is higher than the isolation region.
13. The method of claim 11 , where non-selectively depositing silicon comprises forming polysilicon on the isolation region.
14. The method of claim 11 , further comprising:
forming a first gate electrode structure over the first epitaxial semiconductor layer, said first gate electrode structure comprising at least a first gate dielectric layer and a first conductive layer; and
forming a second gate electrode structure over the second semiconductor layer, said second gate electrode structure comprising at least a second gate dielectric layer and a second conductive layer.
15. The method of claim 12 , where non-selectively depositing silicon comprises forming polysilicon on the mask layer.
16. A method for fabricating a semiconductor structure having substantially uniform dual-surface orientation substrate heights, comprising:
forming first and second semiconductor substrates that are electrically isolated from each other by at least a first isolation region, where the first semiconductor substrate has a first crystallographic orientation and where the second semiconductor substrate has a second crystallographic orientation that is different from the first crystallographic orientation;
blanket depositing silicon to form a polysilicon layer over the first isolation region and to form a crystalline silicon layer on at least the first semiconductor substrate; and
polishing the first semiconductor substrate and the polysilicon layer so that the first semiconductor substrate is substantially coplanar with the second semiconductor substrate.
17. The method of claim 16 , where forming first and second semiconductor substrates comprises:
forming a first semiconductor layer having a first crystal orientation;
forming a second semiconductor substrate over at least part of the first semiconductor layer, where the second semiconductor substrate has a second crystal orientation that is different from the first crystal orientation and where the second semiconductor substrate is electrically isolated from the first semiconductor layer by a buried insulator layer;
forming a trench opening to expose at least a portion of the first semiconductor layer; and
epitaxially growing a first epitaxial semiconductor material on at least an exposed surface of the first semiconductor layer to form a first semiconductor substrate having the first crystal orientation.
18. The method of claim 16 , where the second semiconductor substrate comprises (110) or (100) p-type silicon, the first semiconductor substrate comprises (100) or (110) n-type silicon.
19. The method of claim 16 , where the first isolation region is formed prior forming the first semiconductor substrate.
20. The method of claim 16 , where the first isolation region is formed after forming the first semiconductor substrate.