Method of manufacturing a semiconductor component
View Patent ↗A semiconductor component comprises a first semiconductor region ( 110, 310 ), a second semiconductor region ( 120, 320 ) above the first semiconductor region, a third semiconductor region ( 130, 330 ) above the second semiconductor region, a fourth semiconductor region ( 140, 340 ) above the third semiconductor region, a fifth semiconductor region ( 150, 350 ) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region ( 160, 360 ) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer ( 180, 380 ) above the fourth semiconductor region and the fifth semiconductor region. A junction ( 145, 345 ) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region ( 170 ) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
1. A method of manufacturing a semiconductor component, the method comprising:
providing a composite semiconductor substrate comprising:
a substrate having a first conductivity type;
a buried layer having a second conductivity type above the substrate; and
a semiconductor epitaxial layer above the buried layer;
forming a first semiconductor region having a conductivity type in the semiconductor epitaxial layer to define a second semiconductor region in the semiconductor epitaxial layer, the second semiconductor region circumscribed by the first semiconductor region and having a doping level less than a doping level of the first semiconductor region;
forming an electrically insulating layer above the semiconductor epitaxial layer, a first portion of the semiconductor epitaxial layer covered by the electrically insulating layer, and a second portion and a third portion of the semiconductor epitaxial layer not covered by the electrically insulating layer;
forming a third semiconductor region having a conductivity type different from the conductivity type of the first semiconductor region, located in the second portion of the semiconductor epitaxial layer and above the second semiconductor region, at least partially contiguous with the first semiconductor region, and having a doping level greater than a doping level of the first semiconductor region;
forming a fourth semiconductor region having the conductivity type of the first semiconductor region located in the third portion of the semiconductor epitaxial layer and electrically shorted to the first semiconductor region; and
forming a fifth semiconductor region having the second conductivity type, at least partially contiguous with the buried layer, and circumscribing the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region,
wherein:
a junction between the third semiconductor region and the first semiconductor region forms a zener diode junction; and
the zener diode junction is located only underneath the electrically insulating layer.
2. The method of claim 1 further comprising:
forming the first semiconductor region to have a doping level lower than doping levels of the buried layer, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region.
3. The method of claim 1 wherein:
forming the electrically insulating layer occurs before forming the third semiconductor region and the fourth semiconductor region.
4. The method of claim 3 wherein:
forming the third semiconductor region further comprises:
self-aligning the third semiconductor region to the electrically insulating layer; and
forming the fourth semiconductor region further comprises:
self-aligning the fourth semiconductor region to the electrically insulating layer.
5. The method of claim 1 wherein:
forming the third semiconductor region and the fourth semiconductor region occur before forming the electrically insulating layer.
6. A method of manufacturing a semiconductor component, the method comprising:
providing a composite semiconductor substrate comprising:
a substrate having a first conductivity type;
a buried layer having a second conductivity type above the substrate; and
a semiconductor epitaxial layer above the buried layer;
forming a first semiconductor region having the second conductivity type in the semiconductor epitaxial layer to define a second semiconductor region in the semiconductor epitaxial layer, the second semiconductor region circumscribed by the first semiconductor region and having a doping level less than a doping level of the first semiconductor region, the first semiconductor region contacting the buried layer;
forming an electrically insulating layer above the semiconductor epitaxial layer, a first portion of the semiconductor epitaxial layer covered by the electrically insulating layer, and a second portion and a third portion of the semiconductor epitaxial layer not covered by the electrically insulating layer;
forming a third semiconductor region having the first conductivity type in the second portion of the semiconductor epitaxial layer and above the second semiconductor region, at least partially contiguous with the first semiconductor region, and having a doping level greater than a doping level of the first semiconductor region; and
forming a fourth semiconductor region having the second conductivity type in the third portion of the semiconductor epitaxial layer and electrically shorted to the first semiconductor region,
wherein:
a junction between the third semiconductor region and the first semiconductor region forms a zener diode junction; and
the zener diode junction is located only underneath the electrically insulating layer.
7. The method of claim 6 further comprising:
forming the first semiconductor region to have a doping level lower than doping levels of the buried layer, the third semiconductor region, and the fourth semiconductor region.
8. The method of claim 6 wherein:
forming the electrically insulating layer occurs before forming the third semiconductor region and the fourth semiconductor region.
9. The method of claim 8 wherein:
forming the third semiconductor region further comprises:
self-aligning the third semiconductor region to the electrically insulating layer; and
forming the fourth semiconductor region further comprises:
self-aligning the fourth semiconductor region to the electrically insulating layer.
10. The method of claim 6 wherein:
forming the third semiconductor region and the fourth semiconductor region occur before forming the electrically insulating layer.