Granted Patent B2

US 6,862,240 · App. 10/878,956 · Granted Mar 1, 2005

Abstract

Claims (18)

1. A memory comprising:

a plurality of memory cells that require periodic refreshing to maintain stored data;

a variable refresh control circuit comprising a plurality of test memory cells, each of the plurality of test memory cells including a capacitor for storing charge representative of a stored logic state, the plurality of test memory cells being refreshed at a predetermined refresh rate, and each of the plurality of test memory cells being implemented to store a different amount of charge than other test memory cells of the plurality of test memory cells; and

a monitor circuit for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting a refresh rate of the plurality of memory cells.

2. The memory of claim 1 wherein a charge storage ability of one test cell of the plurality of test memory cells is greater than a charge storage ability of each of the plurality of memory cells for the predetermined refresh rate.

3. The memory of claim 1 , wherein the plurality of memory cells and the plurality of test memory cells are dynamic random access memory (DRAM) cells.

4. The memory of claim 1 , further comprising a sense amplifier coupled to a first test cell of the plurality of test memory cells, the first test cell having a charge storage ability that is greater than a charge storage ability of one of the plurality of memory cells, the sense amplifier providing a signal for indicating if the predetermined refresh rate is sufficient for reliably maintaining a stored logic state of the first test cell.

5. The memory of claim 4 , wherein if the predetermined refresh rate is not sufficient for reliably maintaining the stored logic state of the first test cell, increasing the refresh rate of the plurality of memory cells.

6. The memory of claim 1 , wherein the plurality of test memory cells are organized as pairs of test memory cells, wherein a pair of test memory cells includes a first test cell and a second test cell, the first test cell for storing a high logic state and the second test cell for storing a low logic state, the each test cell of the pair of test memory cells having a charge leakage rate that is greater than a charge leakage rate of one of the plurality of memory cells.

7. The memory of claim 1 , wherein the plurality of test memory cells include a first test cell and a second test cell, the first test cell having a first charge storage ability that is greater than a charge storage ability of one of the plurality of memory cells, the second test cell having a second charge storage ability that is greater than the first charge storage ability.

8. The memory of claim 1 , wherein the plurality of test memory cells and the plurality of memory cells are implemented together on a single integrated circuit.

9. A method for refreshing a memory array having a plurality of

memory cells for storing data, comprising the steps of:

providing a plurality of test memory cells, each of the plurality of test memory cells being implemented to have different charge storage ability than other test memory cells of the plurality of test memory cells;

refreshing the test memory cells at a predetermined refresh rate;

monitoring the charge storage ability of the plurality of test memory cells; and

adjusting the refresh rate of the memory array in response to the monitoring of the charge storage ability of the plurality of test memory cells.

10. The method of claim 9 , where the step of monitoring the charge storage ability of the plurality of test memory cells further comprises monitoring the ability of the plurality of test memory cells to maintain a predetermined minimum voltage maginitude.

Assignments (17)