Memory access with consecutive addresses corresponding to different rows
View Patent ↗A memory system ( 200 ) has an array of addressable storage elements ( 210 ) arranged in a plurality of rows and a plurality of columns, and decoding circuitry ( 220, 230 ) coupled to the array of addressable storage elements ( 210 ). The decoding circuitry ( 220, 230 ), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.
1. A memory system comprising:
an array of addressable storage elements arranged in a plurality of rows and a plurality of columns, wherein the array of addressable storage elements comprises a plurality of nonvolatile memory cells; and
decoding circuitry coupled to the array of addressable storage elements, the decoding circuitry, responsive to decoding a first element address, to access a first storage element of a first row of the plurality of rows, mid the decoding circuitry, responsive to decoding a second element address consecutive to the first element address, to access a second storage element of a second row of the plurality of rows, the second row of the plurality of rows different from the first row of the plurality of rows;
wherein the first address comprises a group of bits;
wherein the second address comprises a group of bits;
wherein the decoding circuitry includes a row decoder and a column decoder;
wherein the row decoder is operable responsive to a first portion of the group of bits of the first address and the second address;
wherein the column decoder is operable responsive to a second portion of the group of bits of the first address and the second address, wherein a bit of the second portion is more significant than a bit of the first portion.
2. A memory system according to claim 1 wherein each of the storage elements stores one bit.
3. A memory system according to claim 1 wherein each of the storage elements stores a plurality of bits arranged as a word.
4. A memory system according to claim 1 wherein each of the storage elements stores a plurality of bits arranged as a page.
5. The memory system of claim 1 wherein each bit of the second portion is more significant than a least significant bit of the first portion.
6. A memory system according to claim 1 wherein each of the plurality of nonvolatile memory cells comprises a floating gate-type cell.
7. A memory system according to claim 1 wherein each of the plurality of nonvolatile memory cells comprises an EEPROM cell.
8. A memory system comprising:
an array of storage elements arranged in a plurality of rows and a plurality of columns, each of the storage elements comprising an input and an output, each of the storage elements corresponding to a numeric address comprising more significant bits and less significant bits, wherein the array of storage elements comprises a plurality of nonvolatile memory cells;
decoder circuitry operable responsive to a plurality of numeric addresses, including a first numeric address and a second numeric address, the second numeric address consecutive to the first numeric address, the decoder circuitry including:
a column decoder coupled to the outputs of the storage elements of each of the plurality of columns, the column decoder operable responsive to at least one of the more significant bits, the column decoder operable responsive to a portion of the first numeric address and a nortion of the second numeric address; and
a row decoder coupled to the inputs of the storage elements of each of the plurality of rows, the row decoder operable responsive to at least one of the less significant bits, the row decoder operable responsive to a portion of the first numeric address and a portion of the second numeric address.
9. A memory system according to claim 8 wherein
the input of each of the storage elements is a control gate, and
the output of each of the storage elements is a drain.
10. A memory system according to claim 8 wherein each of the storage elements stores one bit.
11. A memory system according to claim 8 wherein each of the storage elements stores a plurality of bits arranged as a word.
12. A memory system according to claim 8 wherein each of the storage elements stores a plurality of bits arranged as a page.
13. A memory system according to claim 8 wherein each of the plurality of nonvolatile memory cells comprises a floating gate-type cell.
14. A memory system according to claim 8 wherein the at least one of the less significant bits comprises all of the less significant bits.
15. The memory system of claim 8 wherein:
the numeric address comprises a group of bits;
the row decoder is operable responsive to a first portion of the group of bits;
the column decoder is operable responsive to a second portion of the group of bits, wherein each bit of the second portion is more significant than a least significant bit of the first portion.
16. A memory system according to claim 8 wherein each of the plurality of nonvolatile memory cells comprises an EEPROM cell.
17. An embedded control system comprising:
a processor; and
a memory system coupled to the processor, the memory system comprising an input to receive an address signal from the processor, an output to send addressed infonnation to the processor, and a plurality of blocks, each of the plurality of blocks comprising:
an array of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns to store information within a plurality of pages, each of the plurality of pages comprising a plurality of words, each of the plurality of words comprising a plurality of bits; and
decoding circuitry comprising a cohumn decoder and a row decoder, the decoding circuitry coupled to the input, the output and the array of nonvolatile memory cells, the decoding circuitry, responsive to the address signal having a first page address, accessing a first page of a first row of the plurality of rows, the decoding circuitry, responsive to the address signal having a second page address consecutive to the first page address, accessing a second page of a second row of the plurality of rows, and, thereafter, the decoding circuitry coupling the first and second pages to the output;
wherein each address comprises a group of bits;
wherein the row decoder is operable responsive to a first portion of the group of bits;
wherein the column decoder is operable responsive to a second portion of the group of bits, wherein a bit of the second portion is more significant than a bit of the first portion.
18. The embedded control system of claim 17 , wherein at least one bit of the group of bits is representative of addresses of the plurality of blocks.
19. An embedded control system according to claim 17 wherein each memory cell of the array of nonvolatile memory cells comprises a floating gate-type cell.
20. An embedded control system according to claim 17 wherein each memory cell of the array of nonvolatile memory cells comprises an EEPROM cell.
21. An embedded control system comprising:
a processor; and
a memory system coupled to the processor, the memory system comprising an input to receive an address signal from the processor, an output to send addressed information to the processor, and a plurality of blocks, each of the plurality of blocks comprising:
an array of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns to store information within a plurality of pages, each of the plurality of pages comprising a plurality of words, each of the plurality of words comprising a plurality of bits; and
decoding circuitry comprising a column decoder and a row decoder, the decoding circuitry coupled to the input, the output and the array of nonvolatile memory cells, the decoding circuitry, responsive to the address signal having a first page address, accessing a first page of a first row of the plurality of rows, the decoding circuitry, responsive to the address signal having a second page address consecutive to the first page address, accessing a second page of a second row of the plurality of rows, and, thereafter, the decoding circuitry coupling the first and second pages to the output;
wherein the address signal comprises:
least significant bits representative of addresses of bits within a word,
next least significant bits representative of addresses of words within a page,
intermediate significant bits representative of addresses of the plurality of rows, the intermediate significant bits more significant than the next least significant bits,
more significant bits representative of addresses of pages within the plurality of rows, the more significant bits more significant than tbe intermediate significant bits, and
next more significant bits representative of addresses of the plurality of blocks, the next more significant bits more significant than the more significant bits.
22. A method of accessing a memory system, the memory system comprising an array of addressable storage elements arranged in a plurality of rows and a plurality of columns, wherein the array of addressable storage elements comprises a plurality of nonvolatile memory cells, the method comprising:
decoding a first element address;
accessing, responsive to the first element address, a first storage element of a first row of the plurality of rows;
decoding a second element address, the second element address consecutive to the first element address; and
accessing, responsive to the second element address, a second storage element of a second row of the plurality of rows, the second row of the plurality of rows different from the first row of the plurality of rows;
wherein the first element address includes a group of bits;
wherein the decoding the first element address further includes decoding a first portion of the group of bits by a row decoder and decoding a second portion of the group of bits by a column decoder;
wherein a bit of the second portion is more significant than a bit of the first portion.
23. A method according to claim 22 wherein accessing a first storage element comprises reading a first page, the first page comprising a plurality of bits.
24. A method according to claim 23 wherein accessing a second storage element comprises reading a second page different from the first page, the second page comprising a plurality of bits.
25. A method according to claim 22 wherein accessing a first storage element comprises initiating a first burst access, the first burst access comprising a plurality of bits.
26. A method according to claim 25 wherein accessing a second storage element comprises initiating a second burst access different from the first burst access, the second burst access comprising a plurality of bits.
27. The method of claim 22 wherein each bit of the second portion is more significant than a least significant bit of the first portion.
28. A method according to claim 22 wherein each of the plurality of nonvolatile memory cells comprises a floating gate-type cell.
29. A method according to claim 22 wherein each of the plurality of nonvolatile memory coils comprises an EEPROM cell.
30. An embedded control system comprising:
a processor; and
a memory system coupled to the processor, the memory system comprising an input to receive an address signal from the processor, an output to send addressed information to the processor, and a plurality of blocks, each of the plurality of blocks comprising:
an array of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns to store infonnation within a plurality of pages, each of the plurality of pages comprising a plurality of words, each of the plurality of words comprising a plurality of bits; and
decoding circuitry comprising a column decoder and a row decoder, the decoding circuitry coupled to the input, the output and the array of nonvolatile memory cells, the decoding circuitry, responsive to the address signal having a first page address, accessing a first page of a first row of the plurality of rows, the decoding circuitry, responsive to the address signal having a second page address consecutive to the first page address, accessing a second page of a second row of the plurality of rows, and, thereafter, the decoding circuitry coupling the first and second pages to the output;
wherein:
the address signal comprises a group of bits;
the row decoder is operable responsive to a first portion of the group of bits;
the column decoder is operable responsive to a second portion of the group of bits, wherein each bit of the second portion is more significant than a least significant bit of the first portion.
31. An embedded control system according to claim 30 wherein each memory cell of the array of nonvolatile memory cells comprises a floating gate-type cell.
32. An embedded control system according to claim 30 wherein each memory cell of the array of nonvolatile memory cells comprises an EEPROM cell.
33. A memory system comprising an input to receive an address signal, an output to send addressed information, and a plurality of blocks, each of the plurality of blocks comprising:
an array of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns to store information within a plurality of pages, each of the plurality of pages comprising a plurality of words, each of the plurality of words comprising a plurality of bits; and
decoding circuitry comprising a column decoder and a row decoder, the decoding circuitry coupled to the input, the output and the array of nonvolatile memory cells, the decoding circuitry, responsive to the address signal having a first page address, accessing a first page of a first row of the plurality of rows, the decoding circuitry, responsive to the address signal having a second page address consecutive to the first page address, accessing a second page of a second row of the plurality of rows, and, thereafter, the decoding circuitry coupling the first and second pages to the output;
wherein the address signal comprises:
a first group of bits representative of addresses of the plurality of rows,
a second group of bits representative of addresses of pages within the plurality of rows, wherein the second group includes a bit more significant than a bit of the first group;
a third group of at least one bit representative of addresses of the plurality of blocks.
34. A memory system according to claim 33 wherein each memory cell of the away of nonvolatile memory cells comprises a floating gate-type cell.
35. A memory system according to claim 33 wherein each memory cell of the array of nonvolatile memory cells comprises an EEPROM cell.