Method and system for improving the manufacturability of integrated circuits
View Patent ↗At a particular stage in design of an integrated circuit, DFM improvements are identified which might conflict with design requirements applicable during a subsequent stage in the design flow. These DFM improvements are “reserved” that is, they are not implemented right away. However, an instance of a DFM-optimized version of this portion of the design is generated, characterized and stored. Meta information is associated with the reserved DFM improvements, for example locations in the design which correspond to the reserved DFM improvements are tagged. If, after the subsequent stage in the design flow, processing of the meta-information (tags) shows that the reserved DFM improvement does not actually conflict with the potentially-conflicting design requirement, the corresponding reserved DFM improvement is implemented, for example, by swapping-in the stored instance of the DFM-optimized version of this portion of the design.
1. An integrated-circuit design method implementing a series of design stages to generate, in the final design stage of said series, design data defining an integrated circuit, each of the design stages processing design stage representing the design-in-progress, said integrated-circuit design method comprising a process for improving the manufacturability of the integrated circuit by:
during at least one design stage of said series, identifying, in a portion of the design-in-progress, a set of one or more DFM improvements that could be made, at least one DFM improvement in said set potentially conflicting with a design requirement applicable during a later design stage in said series;
deferring said at least one potentially-conflicting DFM improvement such that said potentially-conflicting DFM improvement is not implemented during the design stage where it is first identified;
determining, during said later design stage, whether or not at least one potentially-conflicting DFM improvement identified and deferred at an earlier design stage actually conflicts with one or more design requirements applicable during said later design stage; and
implementing, in the design, said deferred at least one potentially conflicting DFM improvement only after it has been determined, in said determining step during said later design stage, that there is no actual conflict with said specified one or more design requirements, and wherein:
said manufacturability-improving process comprises the step of identifying, in said portion of the design-in-progress performed by an integrated-circuit design system, a region or regions that would be affected by a particular DFM improvement of said set; and
the determining step of said manufacturability-improving process comprises verifying whether there are any of said identified regions that are unaffected by said one or more design requirements, and deciding that the DFM improvement(s) corresponding to said unaffected identified region(s) does (do) not conflict with said one or more design requirements, wherein:
said one or more design requirements comprise the requirement for a region affected by a DFM improvement not to overlap with, or be within a predetermined distance of, a connection track;
said region-identifying step comprises the step of tagging segments of candidate paths for connection tracks, the tagged segments of the candidate paths corresponding to segments of the candidate paths which overlap with or are within a predetermined distance of a region affected by a DFM improvement, and
the verifying step comprises verifying, after routing to said portion of the design-in-progress has been performed, which tagged segments of candidate paths for connection tracks have not been used for routing.
2. The integrated-circuit design method of claim 1 , wherein:
said manufacturability-improving process comprises the step of generating meta-information associated with respective DFM improvements of the set, and
said determining step is adapted to process meta-information associated with a particular DFM improvement whereby to determine whether or not said particular DFM improvement actually conflicts with said one or more design requirements.
3. The integrated-circuit design method of claim 1 , wherein:
said manufacturability-improving process comprises the step of, during said at least one design stage, generating and storing a reserved instance of said portion of the design-in-progress, said reserved instance corresponding to said portion of the design-in-progress modified to include some or all of the DFM improvements of said set, wherein said reserved instance is not incorporated into the design-in-progress during the design stage where it is generated; and
the improvement-implementing step of said manufacturability-improving process comprises swapping, for said portion of the design-in-progress, a reserved instance including one or more DFM improvements, of said set, which have been determined during said later design stage not to conflict with said one or more design requirements.
4. The integrated-circuit design method of claim 3 , wherein:
said manufacturability-improving process comprises the step of generating and storing data characterizing said reserved instance; and
the improvement-implementing step of said manufacturability-improving process comprises a step of analysing the data characterizing a reserved instance so as to ensure that swapping said reserved instance for said portion of the design-in-progress will not have an adverse effect on the functioning of the circuit under design.
5. The integrated-circuit design method of claim 1 , wherein said portion of the design-in-progress corresponds to a cell of the integrated circuit under design.
6. The integrated-circuit design method of claim 1 , wherein the process for improving manufacturability is applied a plurality of times during the design of the overall circuit, each application of the manufacturability-improvement process comprising the identification, at a respective first stage in the design flow, of a set of one of more DFM improvements that potentially conflict with a respective set of design requirements applicable during a respective second stage of the design flow, and the implementation, at the respective second stage, of one or more of the respective set of DFM improvements which are determined, at said respective second stage, not to conflict with the respective set of design requirements; wherein the second stage of each application of the manufacturability-improvement process is subsequent to the first stage thereof.
7. An integrated-circuit design system for implementing a series of design stages to generate, in the final design stage of said series, design data defining an integrated circuit, each of the design stages processing design data representing the design-in-progress, said integrated-circuit design system comprising:
identification means for identifying during at least one design stage of said series, in a portion of the design-in-progress, a set of one or more DFM improvements that could be made, at least one DFM improvement in said set potentially conflicting with a design requirement applicable during a later design stage in said series, said at least one DFM improvement being deferred;
determining means for determining, at said later design stage, whether or not at least one potentially-conflicting DFM improvement identified by the identification means at an earlier design stage, and deferred, actually conflicts with one or more design requirements applicable during said later design stage; and
execution means for implementing, in the design, said deferred at least one potentially-conflicting DFM improvement only after it has been determined by said determining means in said later design stage that there is no actual conflict with said one or more design requirements and wherein:
said tagging means is adapted for generating meta-information indicative of a region or regions that would be affected by a particular DFM improvement of said set;
wherein the determining means is adapted to verify whether there are any of said identified regions that are unaffected by said one or more design requirements, and to decide that the DFM improvement(s) corresponding to said unaffected identified region(s) does (do) not conflict with said one or more design requirements, wherein:
said one or more design requirements comprise the requirement for a region affected by a DFM improvement not to overlap with, or be within a predetermined distance of, a connection track;
said tagging means is adapted to tag segments of candidate paths for connection tracks, the tagged segments of the candidate paths corresponding to segments of the candidate paths which overlap with or are within a predetermined distance of a region affected by a DFM improvement, and
the determining means is adapted to verify, after routing to said portion of the design-in-progress has been performed, which tagged segments of candidate paths for connection tracks have not been used for routing.
8. The integrated-circuit design system of claim 7 , and comprising:
tagging means for generating and associating meta-information with respective DFM improvements of said set during said at least one design stage;
wherein the determining means is adapted to process the meta-information associated with a particular DFM improvement whereby to determine whether or not said particular DFM improvement actually conflicts with said one or more design requirements.
9. The integrated-circuit design system of claim 7 , and comprising means for generating and storing a reserved instance of said portion of the design-in-progress during said at least one stage, said reserved instance corresponding to said portion of the design-in-progress modified to include some or all of the DFM improvements of said set;
wherein the execution means is adapted to swap, for said portion of the design-in-progress, a reserved instance including one or more DFM improvements, of said set, which have been determined during said later design stage not to conflict with said one or more design requirements.
10. The integrated-circuit design system of claim 9 , and comprising means for generating and storing data characterizing said reserved instance;
wherein the execution means comprises analysis means for analysing the data characterizing a reserved instance so as to ensure that swapping said reserved instance for said portion of the design-in-progress will not have an adverse effect on the functioning of the circuit under design.
11. The integrated-circuit design system of claim 7 , wherein said portion of the design-in-progress corresponds to a cell of the integrated circuit under design.
12. The integrated-circuit design system of claim 7 , and comprising a plurality of sets of identification means, determining means and execution means, each set performing a respective manufacturability-improvement process.