Granted Patent B2

US 8,193,572 · App. 12/647,250 · Granted Jun 5, 2012

Abstract

Claims (44)

1. An electronic device comprising:

a substrate including a portion that defines a first trench having a first bottom, a first wall, and a second wall opposite the first wall;

a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench;

a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench, wherein the first gate electrode lies between the first wall and the second gate electrode;

a first set of discontinuous storage elements, wherein the first set of discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench;

a third gate electrode within the first trench and adjacent to the second wall and overlying the first bottom of the first trench;

a fourth gate electrode within the first trench and adjacent to the third gate electrode and overlying the first bottom of the first trench, wherein the third gate electrode being between the second wall and the fourth gate electrode;

a second set of discontinuous storage elements, wherein the second set of discontinuous storage elements lies between (i) the third gate electrode or the fourth gate electrode and (ii) the first bottom of the first trench; and

wherein a first memory cell comprises the first gate electrode, the second gate electrode, and the first set of discontinuous storage elements; a second memory cell comprises the third gate electrode, the fourth gate electrode, and the second set of discontinuous storage element; and the second gate electrode being between the first gate electrode and the fourth gate electrode.

2. The electronic device of claim 1 , wherein the second gate electrode is conformal to the first gate electrode.

3. The electronic device of claim 2 , wherein:

the first gate electrode is a select gate electrode;

the second gate electrode is a control gate electrode; and

the first set of the discontinuous storage elements only lies between the second gate electrode and the bottom of the first trench, and substantially no discontinuous storage elements lie between the second gate and the first wall.

4. The electronic device of claim 2 , further comprising a first source/drain region and a second source/drain region, wherein:

the substrate has a primary surface;

the first source/drain region lies within the substrate and adjacent to the primary surface and the first wall of the first trench; and

the second source/drain region lies within the substrate and adjacent to the bottom of the first trench and is spaced apart from the first wall of the first trench.

5. The electronic device of claim 1 , wherein within the first memory cell, substantially all of the first and second gate electrodes lie within the first trench.

6. The electronic device of claim 1 , wherein each of the first gate electrode and the second gate electrode has a shape, which from a cross-sectional view, is a sidewall spacer.

7. The electronic device of claim 1 , further comprising a fifth gate electrode, a sixth gate electrode, and a third set of discontinuous storage elements, wherein: the substrate including another portion that defines a second trench having a second bottom and a second wall; the fifth gate electrode lies within the second trench and adjacent to the second wall and overlying the second bottom of the second trench; the sixth gate electrode lies within the second trench and adjacent to the fifth gate electrode and overlying the second bottom of the second trench; and the third set of the discontinuous storage elements lies between (i) the second bottom of the second trench and (ii) the fifth gate electrode or the sixth gate electrode.

8. The electronic device of claim 7 , further comprising a first source/drain region, a second source/drain region, and a third source/drain region, wherein:

the substrate has a primary surface;

the first source/drain region lies within the substrate and adjacent to the primary surface, the first wall of the first trench, and the second wall of the second trench;

the second source/drain region lies within the substrate and adjacent to the bottom of the first trench and is spaced apart from the first wall of the first trench; and

the third source/drain region lies adjacent to the bottom of the second trench and is spaced apart from the second wall of the second trench.

9. An electronic device comprising: a substrate including a portion that defines a first trench having a bottom, a first wall, and a second wall opposite the first wall; a first gate electrode within the first trench and adjacent to the first wall and overlying the bottom of the first trench; a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the bottom of the first trench, wherein the first gate electrode lies between the first wall and the second gate electrode; and a first set of discontinuous storage elements, wherein the set of discontinuous storage elements lies between the first gate electrode and the bottom of the first trench; a third gate electrode within the first trench and adjacent to the second wall and overlying the bottom of the first trench; a fourth gate electrode within the first trench and adjacent to the third gate electrode and overlying the bottom of the first trench, wherein the third gate electrode being between the second wall and the fourth gate electrode; a second set of discontinuous storage elements, wherein the second set of discontinuous storage elements lies between (i) the third gate electrode or the fourth gate electrode and (ii) the first bottom of the first trench; and wherein a first memory cell comprises the first gate electrode, the second gate electrode, and the first set of discontinuous storage elements; a second memory cell comprises the third gate electrode, the fourth gate electrode, and the second set of discontinuous storage element; and the second gate electrode being between the first gate electrode and the fourth gate electrode.

10. The electronic device of claim 9 , wherein substantially no discontinuous storage element lies between a bottom surface of the second gate electrode and the bottom of the first trench.

11. The electronic device of claim 9 , wherein:

within the first memory cell, substantially all of the first and second gate electrodes lie within the first trench;

the substrate includes other portions that define other trenches and other sets of discontinuous storage elements lying within the other trenches; and

substantially all of the discontinuous storage elements lie within the first and other trenches.

12. An electronic device comprising: a substrate including a portion that defines a first trench having a bottom and a first wall and a second wall opposite the first wall; a first gate electrode within the first trench and adjacent to the first wall and overlying the bottom of the first trench; a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the bottom of the first trench; wherein the first gate electrode lies between the first wall and the second gate electrode; and a first set of discontinuous storage elements, wherein the set of discontinuous storage elements lies between the second gate electrode and the bottom of the first trench; a third gate electrode within the first trench and adjacent to the second wall and overlying the bottom of the first trench; a fourth gate electrode within the first trench and adjacent to the third gate electrode and overlying the bottom of the first trench, wherein the third gate electrode being between the second wall and the fourth gate electrode; a second set of discontinuous storage elements, wherein the second set of discontinuous storage elements lies between (i) the third gate electrode or the fourth gate electrode and (ii) the first bottom of the first trench; and wherein a memory cell comprises the first gate electrode, the second gate electrode, and the set of discontinuous storage elements, a second memory cell comprises the third gate electrode, the fourth gate electrode, and the second set of discontinuous storage element; and the second gate electrode being between the first gate electrode and the fourth gate electrode.

13. The electronic device of claim 12 , wherein:

the first gate electrode is a select gate electrode;

the second gate electrode is a control gate electrode; and

the first set of discontinuous storage elements is spaced apart from the wall of the first trench.

14. The electronic device of claim 13 , wherein within the device, substantially all of the first, second, third, and fourth gate electrodes lie within the first trench.

15. The electronic device of claim 14 , wherein substantially no discontinuous storage element lies between the first gate electrode and the bottom of the first trench.

16. The electronic device of claim 12 , wherein substantially no discontinuous storage element lies between the first gate electrode and the bottom of the first trench.

17. The electronic device of claim 12 , wherein:

the substrate includes other portions that define other trenches;

other sets of discontinuous storage elements lie within the other trenches; and

substantially all of the discontinuous storage elements of a memory array that includes the first and second memory cells lie within the first and other trenches.

Assignments (24)