Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit
View Patent ↗An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.
1. An integrated circuit, comprising:
a first transistor of a first conductivity type, including a first strained transistor channel, wherein the first transistor is characterized by a first value of stress along a first axis and a second value of stress along a second axis that is perpendicular to the first axis;
a first stressor overlying the first transistor;
a second transistor of a second conductivity type, including a second strained transistor channel, wherein the second strained transistor channel is characterized by a third value of stress along the first axis and a fourth value of stress along the second axis;
wherein the first, second, and fourth values are tensile stress values and the third value is a compressive stress value; and
a second stressor overlying the second transistor, wherein a source/drain region displaced on either side of the first strained transistor channel is comprised of a semiconductor having a lattice constant that differs from the lattice constant of silicon and the second stressor is different than the first stressor.
2. The integrated circuit of claim 1 , wherein magnitudes of the first and fourth values exceed a magnitude of the second value.
3. The integrated circuit of claim 1 , wherein a source/drain region displaced on either side of the first strained transistor channel is comprised of a semiconductor having a lattice constant that differs from the lattice constant of silicon.
4. The integrated circuit of claim 1 , wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.
5. The integrated circuit of claim 4 , wherein the first stressor exerts tensile stress on the first strained transistor channel and wherein the second stressor exerts compressive stress on second strained transistor channel.
6. The integrated circuit of claim 4 , wherein the NMOS transistor and the PMOS transistor have a common length (L) value and a common value of effective width (W), and further wherein the NMOS and PMOS transistor differ in a value of a parameter selected from the list consisting of length of diffusion region (SA) and width of source/drain (WS).
7. The integrated circuit of claim 6 , wherein the NMOS transistor has a value of WS that is greater than a WS value of the PMOS transistor and wherein the NMOS transistor includes a plurality of channel dielectric structures underlying a transistor gate electrode.
8. The integrated circuit of claim 6 , wherein the PMOS transistor has an SA value that is less than an SA value of the NMOS transistor.
9. The integrated circuit of claim 6 wherein the PMOS transistor has an SA value that is less than an SA value of the NMOS transistor.
10. An integrated circuit, comprising:
a first transistor of a first conductivity type having a first strained transistor channel underlying a first gate electrode;
a first stressor overlying the first transistor;
a second transistor of a second conductivity type having a second strained transistor channel underlying a second gate electrode, wherein a length (L) of the first transistor is substantially equal to an L of the second transistor and further wherein an effective width (W) of the first transistor is substantially equal to an effective width of the second transistor; and
a second stressor overlying the second transistor; wherein the first and second transistors differ in values of at least one parameter selected from the group consisting of length of diffusion (SA) and width of source/drain (WS), wherein the first stressor is different than the second stressor.
11. The integrated circuit of claim 10 , wherein the first transistor has a value of WS that is greater than a WS value of the second transistor and wherein the first transistor includes a plurality of channel dielectric structures underlying a transistor gate electrode.
12. The integrated circuit of claim 10 , wherein the second transistor has an SA value that is less than an SA value of the first transistor.
13. The integrated circuit of claim 10 , wherein the second transistor has an SA value that is less than an SA value of the first transistor.
14. A semiconductor fabrication method, comprising:
forming a first transistor of a first conductivity type, including a first strained transistor channel, wherein the first transistor is characterized by a first value of stress along a channel axis of the first transistor and a second value of stress along a width axis of the first transistor, wherein the channel axis is perpendicular to the width axis and the first transistor is an NMOS transistor;
forming a second transistor of a second conductivity type, including a second strained transistor channel, wherein the second strained transistor channel is characterized by a third value of stress along a channel axis of the second transistor and a fourth value of stress along a width axis of the second transistor and the second transistor is a PMOS transistor; wherein the first, second, and third values of stress comprise first, second, and third tensile stress values and the fourth value of stress comprise a compressive stress value; and
forming a first stressor overlying the NMOS transistor and a second stressor overlying the PMOS transistor, wherein the first stressor exerts tensile stress on the first strained transistor channel and wherein the second stressor exerts compressive stress on second strained transistor channel and the first stressor is different than the second stressor.
15. The semiconductor fabrication method of claim 14 , wherein magnitudes of the first and fourth values exceed a magnitude of the second value.
16. The semiconductor fabrication method of claim 14 , including forming silicon source/drain regions displaced on either side of the first and second strained transistor channels.
17. The semiconductor fabrication method of claim 14 , including forming a source/drain region, displaced on either side of the first strained transistor channel, comprised of a semiconductor having a lattice constant that differs from the lattice constant of silicon.
18. The semiconductor fabrication method of claim 14 , wherein the NMOS transistor and the PMOS transistor have a common length (L) value and a common value of effective width (W), and further wherein the NMOS and PMOS transistor differ in a value of a parameter selected from the list consisting of length of diffusion region (SA) and width of source/drain (WS).