IP Library Granted Patent US 8,976,849
Granted Patent B2
US 8,976,849 · App. 12/523,934 · Granted Mar 10, 2015

Calibration signal generator

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Quick Facts
Patent No.
US 8,976,849
App. No.
12/523,934
Granted
Mar 10, 2015
Kind
B2
Abstract

A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising: a means of amplifying a clocking signal from a clocking signal generator to provide a first calibration signal; a means of generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and a means synchronizing the operation of other circuit elements in the balancing circuit calibration device with the clocking signal; characterized in that the clocking signal generator is present in the radio receiver and used therein for other functions.

Claims (43)

1. A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising:

an amplifier for amplifying a clocking signal from a clocking signal generator to provide a first calibration signal, wherein the amplifier is a squaring amplifier, whose duty cycle is adjustable to control the power in a selected harmonic of the clocking signal;

a quadrature generator for generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and

a synchronizer for synchronising the operation of the balancing circuit calibration device with the clocking signal;

wherein the clocking signal generator is present in the radio receiver.

2. The calibration signal generator as claimed in claim 1 wherein a frequency of the second calibration signal differs from the frequency of the selected harmonic of the clocking signal by an offset frequency being an integer division of a baseband frequency.

3. The calibration signal generator as claimed in claim 2 wherein the balancing circuit calibration device comprises:

a one or more digital local oscillators configured to produce a digital local oscillator (DLO) signal on receipt of the clocking signal from the clocking signal generator;

wherein the frequency of the DLO signal is substantially equal to the offset frequency and is substantially equal to the frequency of the clocking signal divided by a factor; and

wherein the factor is any integer of the form 2 i 0 ×3 i 1 ×5 i 2 where 0<=i 0 <5, 0<=i 1 <2, 0<=i 2 <2).

4. The calibration signal generator as claimed in claim 2 , wherein the balancing circuit calibration device comprises a one or more discrete Fourier transforming components, configured so that the frequency of a digital local oscillator (DLO) signal is substantially equal to a bin frequency of the discrete Fourier transforming components.

5. The calibration signal generator as claimed in claim 4 , wherein the balancing circuit calibration device comprises a one or more analogue to digital converters configured so that a fundamental frequency of an output signal from the analogue to digital converters falls on a bin of the discrete Fourier transforming components.

6. The calibration signal generator of claim 1 , wherein the clocking signal is a master clocking signal of the balancing circuit calibration device.

7. The calibration signal generator as claimed in claim 1 wherein the calibration signal generator is configured to switch to a neighbouring even harmonic or a neighboring odd harmonic in an event that a required signal to noise and power of a present harmonic can not be met.

8. The calibration signal generator as claimed in claim 7 wherein the calibration signal generator is configured to change a divisor of the clocking signal in the event that the required signal to noise and power of the present harmonic can not be met.

9. Method of using a clocking signal generator in a radio receiver, to generate a calibration signal for calibrating the receiver's balancing circuits, the method comprising:

amplifying a clocking signal from the clocking signal generator to produce a first calibration signal;

providing the clocking signal to a synthesiser to generate a second calibration signal therefrom;

ensuring that the frequency of the second calibration signal differs from the frequency of the selected harmonic of the clocking signal by an offset frequency being an integer division of a baseband frequency; and

providing the clocking signal to the balancing circuits, to synchronise their operation.

10. Method as claimed in claim 9 , wherein the step of amplifying the clocking signal comprises the step of adjusting the duty cycle of a squaring amplifier to control a power in a selected harmonic of the clocking signal.

11. Method as claimed in claim 10 wherein the method comprises switching to another harmonic in the event that a required signal to noise and power of the test tone can not be met, the method comprising:

measuring the power in a present harmonic and testing against a predefined threshold limit; and

in the event whereby the threshold is not met switching to a neighbouring even harmonic or a neighbouring odd harmonic; and if required changing the divisor of the clocking signal.

12. Method as claimed in claim 9 wherein the method comprises:

producing a digital local oscillator (DLO) signal from a one or more digital local oscillators on receipt of the clocking signal from the clocking signal generator;

configuring the digital local oscillators so that the frequency of the DLO signal is substantially equal to the offset frequency and is substantially equal to the frequency of the clocking signal divided by a factor being any integer of the form 2 i 0 ×3 i 1 ×5 i 2 where 0<=i 0 <5, 0<=i 1 <2, 0<=i 2 <2).

13. Method as claimed in claim 9 wherein the method comprises:

configuring the digital local oscillators so that the frequency of a digital local oscillator (DLO) signal is substantially equal to a bin frequency of discrete Fourier transforming components in the balancing circuits.

14. The method of claim 9 wherein the clocking signal is provided as a master clocking signal in the radio receiver.

15. The method of claim 9 wherein the providing the clocking signal to the balancing circuits, to synchronise their operation comprises:

providing the clocking signal to a filter in the balancing circuits.

16. The method of claim 15 wherein the providing the clocking signal to the filter in the balancing circuits comprises:

providing the clocking signal via a frequency divider to the filter in the balancing circuits.

17. The method of claim 9 wherein the providing the clocking signal to the balancing circuits, to synchronise their operation comprises:

providing the clocking signal to a digital local oscillator in the balancing circuits.

18. The method of claim 17 wherein the providing the clocking signal to the digital local oscillator in the balancing circuits comprises:

providing the clocking signal via a frequency divider to the digital local oscillator in the balancing circuits.

19. A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising:

an amplifier for amplifying a clocking signal from a clocking signal generator, wherein a selected harmonic of the clocking signal provides a first calibration signal;

a quadrature generator for generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and

a synchronizer for synchronising the operation of the balancing circuit calibration device with the clocking signal; wherein the clocking signal generator is present in the radio receiver;

wherein the calibration signal generator is configured to switch to a neighboring even harmonic or a neighboring odd harmonic as a newly selected harmonic in an event that a required signal to noise and power of the selected harmonic can not be met.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Feb 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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