Method for forming floating gates within NVM process
View Patent ↗A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride ( 20 ) over a semiconductor structure ( 10 ), patterning and etching the nitride layer to form a patterned nitride layer ( 42, 44 ), depositing a layer of polysilicon ( 62 ), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer ( 62 ) above the patterned dielectric layer ( 42, 44 ), and then removing the patterned nitride layer ( 42, 44 ), thereby defining one or more polysilicon features ( 72, 74, 76 ) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.
1. A method for forming a non-volatile memory semiconductor device, comprising:
providing a semiconductor structure;
forming a first dielectric layer over the semiconductor structure;
removing part of the first dielectric layer to leave a patterned dielectric layer over the semiconductor structure;
forming a floating gate layer over the semiconductor structure so that the patterned dielectric layer is substantially completely filled; and
planarizing the semiconductor structure to remove any portion of the floating gate layer above the patterned dielectric layer to define one or more floating gates within the patterned dielectric layer.
2. The method of claim 1 , wherein the semiconductor structure comprises a sacrificial oxide layer formed on a semiconductor substrate.
3. The method of claim 1 , wherein the first dielectric layer comprises a layer of nitride deposited over the semiconductor structure.
4. The method of claim 1 , wherein removing part of the first dielectric layer comprises patterning and etching the first dielectric layer to leave a patterned dielectric layer over the semiconductor structure.
5. The method of claim 1 , wherein removing part of the first dielectric layer comprises patterning and etching one or more masking layers formed on the first dielectric layer to leave a patterned dielectric layer over the semiconductor structure.
6. The method of claim 1 , wherein planarizing the semiconductor structure comprises planarizing the floating gate layer into substantial alignment with an upper surface of the patterned dielectric layer.
7. The method of claim 1 , wherein planarizing the semiconductor structure comprises a chemical mechanical polish process.
8. The method of claim 1 , wherein the one or more floating gates are formed over a tunneling dielectric layer with a polysilicon material, a nanocrystal material, a nitride material or an ONO stack.
9. The method of claim 1 , further comprising removing the patterned dielectric layer after planarizing the semiconductor structure before forming a control gate over the floating gate that is isolated from the floating gate by a control dielectric layer.