IP Library Granted Patent US 8,171,336
Granted Patent B2
US 8,171,336 · App. 12/163,610 · Granted May 1, 2012

Method for protecting a secured real time clock module and a device having protection capabilities

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Quick Facts
Patent No.
US 8,171,336
App. No.
12/163,610
Granted
May 1, 2012
Kind
B2
Abstract

A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than the high frequency of the predefined high frequency code.

Claims (52)

1. A method for protecting a secured real time clock module, the method comprises:

locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration;

unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and

providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked;

wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the multiple input ports of the secured real time clock module;

wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than a high frequency of the predefined high frequency code.

2. The method according to claim 1 wherein the multiple input ports of the secured real time clock module are idle during at least one low-power period, each low-power period of the at least one low-power period being longer than the first duration;

wherein the method comprises generating the predefined high frequency code by a high frequency code generator that is idle during the each low-power period of the at least one low-power period.

3. The method according to claim 1 wherein the multiple input ports of the secured real time clock module are idle during at least one low-power period, the each low-power period of the at least one low-power period being longer than the first duration;

wherein the method comprises receiving the predefined high frequency code by a high frequency code generator that is idle during the at least one low-power period.

4. The method according to claim 1 comprising generating the predefined high frequency code by a high frequency code generator as long as the high frequency code generator receives an enabling signal that is received only during periods that differ from low-power periods.

5. The method according to claim 1 comprising locking the multiple input ports of the secured real time clock module by applying a mask on input signals provided to the multiple input ports of the secured real time clock module; and

wherein the unlocking comprises unmasking the input signals.

6. The method according to claim 1 comprising:

locking the multiple input ports of the secured real time clock module by masking multiple input signals; and

monitoring output ports of a mask in order to determine an activity of the multiple input ports of the secured real time clock module, while ignoring supply voltage induced changes of input signals that are introduced while the multiple input ports of the secured real time clock module are locked.

7. The method according to claim 1 comprising high pass filtering signals sent over the control input port so as to filter out the supply voltage induced changes.

8. A device having secured real time clock module protection capabilities, the device comprises a secured real time clock module; the secured real time clock module comprises:

a controller, coupled to a real time clock generator, adapted to control the real time clock generator in response to control information;

a protection module, coupled to the controller and to multiple input ports of the secured real time clock module, the protection module locks the multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; and unlock the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and

the real time clock generator, adapted to generate a real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked;

wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the multiple input ports of the secured real time clock module;

wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than a high frequency of the predefined high frequency code.

9. The device according to claim 8 wherein the multiple input ports of the secured real time clock module are idle during at least one low-power period, each low-power period of the at least one low-power period being longer than the first duration;

wherein the device further comprises a high frequency code generator that is idle during the each low-power period of the at least one low-power period and is adapted to generate the high frequency code.

10. The device according to claim 9 wherein high frequency code generator generates the high frequency code while it receives an enabling signal; wherein the enabling signal is received only during periods that differ from low-power periods.

11. The device according to claim 8 wherein the protection module comprises a mask; wherein the mask is adapted to mask input signals provided to the multiple input ports of the secured real time clock module; and wherein the mask is adapted to unlock the multiple input ports of the secured real time clock module by unmasking the input signals to the secured real time clock module.

12. The device according to claim 11 comprising a monitor, coupled to output ports of the mask, adapted to monitor the output ports of the mask in order to determine an activity of the multiple input ports of the secured real time clock module, while ignoring supply voltage induced changes of input signals that are introduced while the multiple input ports of the secured real time clock module are locked.

13. The device according to claim 8 comprising a high pass filter adapted to apply a high pass filter operation on signals sent over the control input port so as to filter out the supply voltage induced changes.

14. A method for protecting a secured real time clock module, the method comprises:

locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration;

generating a predefined high frequency code by a high frequency code generator as long as the high frequency code generator receives an enabling signal that is received only during periods that differ from low-power periods; and

unlocking the multiple input ports of the secured real time clock module if the predefined high frequency code is received over a control input port of the secured real time clock module;

wherein a maximal frequency of a supply voltage induced changes of an input signal to the secured real time clock module is lower than a high frequency of the predefined high frequency code.

15. The method according to claim 14 comprising locking the multiple input ports of the secured real time clock module by applying a mask on input signals provided to the multiple input ports of the secured real time clock module; and

wherein the unlocking comprises unmasking the input signals.

16. The method according to claim 14 comprising high pass filtering signals sent over the control input port so as to filter out the supply voltage induced changes.

17. A method for protecting a secured real time clock module, the method comprising:

locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration, wherein the multiple input ports of the secured real time clock module are idle during at least one low-power period, each low-power period of the at least one low-power period being longer than the first duration;

generating a predefined high frequency code by a high frequency code generator that is idle during the each low-power period of the at least one low-power period; and

unlocking the multiple input ports of the secured real time clock module if the predefined high frequency code is received over a control input port of the secured real time clock module;

wherein a maximal frequency of a supply voltage induced changes of an input signal to the secured real time clock module is lower than a high frequency of the predefined high frequency code.

18. A method for protecting a secured real time clock module, the method comprising:

locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration, wherein the multiple input ports of the secured real time clock module are idle during at least one low-power period, the each low-power period of the at least one low-power period being longer than the first duration;

receiving a predefined high frequency code by a high frequency code generator that is idle during the at least one low-power period; and

unlocking the multiple input ports of the secured real time clock module if the predefined high frequency code is received over a control input port of the secured real time clock module;

wherein a maximal frequency of a supply voltage induced changes of an input signal to the secured real time clock module is lower than a high frequency of the predefined high frequency code.

19. A method for protecting a secured real time clock module, the method comprising:

locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module;

wherein a maximal frequency of a supply voltage induced changes of an input signal to the secured real time clock module is lower than a high frequency of the predefined high frequency code;

locking the multiple input ports of the secured real time clock module by masking multiple input signals; and

monitoring output ports of a mask in order to determine an activity of the multiple input ports of the secured real time clock module, while ignoring supply voltage induced changes of input signals that are introduced while the multiple input ports of the secured real time clock module are locked.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0719 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Sep 24, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021570/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2008
From: PRIEL, MICHAEL; KUZMIN, DAN; ZALTZMAN, AMIR
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 021184/0954 →