Method of tiling analog circuits that include resistors and capacitors
View Patent ↗A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.
1. A method for placing tiles in an integrated circuit having matched devices, the method comprising the steps of:
calculating a metal spacing and a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit;
placing tiles based on the metal spacing and the lateral spacing;
performing a density test in sequential areas of the integrated circuit and comparing the metallic density in the areas of the integrated circuit to a predetermined minimum allowable density;
if the metallic density is below the predetermined minimum allowable density, dividing the matched device into at least two subdevices having common centroid arrangement and replacing the previously-placed tiles with new tiles placed substantially around the subdevices at newly determined locations; and
outputting data indicative of the location of the placed tiles.
2. The method according to claim 1 ,
wherein the step of replacing the previously-placed tiles further comprises calculating a metal spacing for tiles to be placed adjacent to the subdevices; and
calculating a lateral spacing for tiles to be placed adjacent to the subdevices; and
placing tiles based on the metal spacing and the lateral spacing.
3. The method according to claim 1 , wherein the step of dividing the matched device further comprises dividing the matched device into subdevices having a predetermined minimum allowable size.
4. The method according to claim 1 , wherein the matched device comprises at least one device selected from the group consisting of poly resistors, diffused resistors, and double-poly capacitors, wherein the device is characterized by an area, and further comprising the step of dividing the device into at least two subdevices, wherein each subdevice has an area, and wherein the combined areas of the subdevices is substantially equivalent to the area of the device.
5. The method according to claim 4 , wherein the step of dividing the device creates lateral spaces between the subdevices and further comprising placing tiles around the subdevices and in the lateral spaces between the subdevices.
6. The method according to claim 1 , wherein the matched device comprises at least one metal-insulator-metal capacitor device having an area, and further comprising the step of dividing the metal-insulator-metal capacitor device into at least two subdevices, wherein each subdevice has an area, and wherein the combined areas of the subdevices is substantially equivalent to the area of the metal-insulator-metal capacitor device.
7. The method according to claim 6 , wherein the step of dividing the metal-insulator-metal capacitor device creates lateral spaces between the subdevices and further comprising placing tiles around the subdevices, in the lateral spaces between the subdevices, and below the subdevices.
8. The method according to claim 7 , wherein the step of placing tiles below the subdevices is characterized by no tiles in the first two layers under each subdevice.
9. The method according to claim 1 , wherein the matched device comprises at least one fringe capacitor device having an area, and further comprising the steps of dividing the fringe capacitor device into at least two subdevices, wherein each subdevice has an area, and wherein the combined areas of the subdevices is substantially equivalent to the area of the fringe capacitor device.
10. The method according to claim 9 , wherein the step of dividing the fringe capacitor creates lateral spaces between subdevices, and further comprising placing tiles in the spaces around all subdevices and wherein placing tiles is characterized by the absence of tiles in the lateral spaces between the subdevices.
11. A system for automatically placing tiles in an integrated circuit having matched devices, the system comprising:
an input device for inputting data to the system;
an output device for outputting data from the system;
a memory; and
a processor linked to the input device, output device, and memory, and wherein the processor is configured so as to calculate a metal spacing for tiles to be placed in proximity to the matched device in the integrated circuit;
calculate a lateral spacing for tiles to be placed in proximity to the matched device in the integrated circuit;
place tiles substantially around the matched device based on the metal spacing and the lateral spacing such that the matched device is substantially surrounded by the placed tiles;
performing a density test in sequential areas of the integrated circuit and comparing the metallic density in the areas of the integrated circuit to a predetermined minimum allowable density;
if the metallic density is below the predetermined minimum allowable density, divide the critically matched device into at least two subdevices having common centroid arrangement, and repeat, with respect to each subdevice, the step to calculate a metal spacing, the step to calculate a lateral spacing, and the step to place tiles; and
outputting data indicative of the location of the placed tiles via the output device.
12. The system according to claim 11 , wherein the matched device comprises at least one resistor device having an area, and wherein the processor is further configured to divide the resistor device into smaller subdevices, wherein each subdevice has an area, and wherein the combined areas of the subdevices is substantially equivalent to the area of the resistor device.
13. The system according to claim 11 , wherein the matched device comprises at least one metal-insulator-metal capacitor device having an area, and wherein the processor is farther configured to divide the metal-insulator-metal capacitor device into smaller subdevices, wherein each subdevice has an area, and wherein the combined areas of the subdevices is substantially equivalent to the area of the metal-insulator-metal capacitor device.
14. The system according to claim 11 , wherein the matched device comprises at least one fringe capacitor device having an area, and wherein the processor is further configured to divide the fringe capacitor device into smaller subdevices, wherein each subdevice has an area, and wherein the combined areas of the subdevices is substantially equivalent to the area of the fringe capacitor device.