IP Library Granted Patent US 7,144,784
Granted Patent B2
US 7,144,784 · App. 10/902,218 · Granted Dec 5, 2006

Method of forming a semiconductor device and structure thereof

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Quick Facts
Patent No.
US 7,144,784
App. No.
10/902,218
Granted
Dec 5, 2006
Kind
B2
Abstract

In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

Claims (54)

1. A method for forming a semiconductor device comprising:

providing a semiconductor substrate having a first portion and a second portion;

forming a first dielectric layer over the first portion of the semiconductor substrate;

forming a second dielectric layer over the second portion of the semiconductor substrate;

forming a cap over the first dielectric;

forming a first gate electrode layer over the cap; and

forming a second gate electrode layer over the second dielectric layer, but not over the first gate electrode layer.

2. The method of claim 1 , wherein forming the first dielectric layer and forming the second dielectric layer comprise forming different dielectric materials.

3. The method of claim 1 , wherein forming the first dielectric layer and forming the second dielectric layer comprise forming the same dielectric material.

4. The method of claim 1 , wherein the forming the first dielectric layer comprises forming a field oxide.

5. The method of claim 1 , wherein forming the first dielectric layer comprises forming a gate dielectric.

6. The method of claim 1 , wherein forming the second dielectric layer comprises forming a dielectric layer with a high dielectric constant.

7. The method of claim 1 , wherein forming the second dielectric layer comprises forming a stack of at least two dielectric layers, wherein at least one of the at least two dielectric layers has a dielectric constant greater than approximately 4.

8. The method of claim 1 , wherein forming the cap comprises forming a polysilicon cap.

9. The method of claim 1 , wherein

the semiconductor substrate further comprises a third portion; and

the method further comprises:

forming a third dielectric layer over the third portion;

forming the second gate electrode layer over the third dielectric layer; and

forming a third gate electrode layer over the second gate electrode layer.

10. The method of claim 9 , wherein forming the third dielectric layer and forming the second dielectric layer comprise forming the same dielectric material.

11. The method of claim 9 , wherein forming the third dielectric layer and forming the second dielectric layer comprise forming different dielectric materials.

12. The method of claim 1 , wherein

the semiconductor substrate further comprises a fourth portion; and

the method further comprises:

forming an isolation region in the fourth portion;

forming the cap over the fourth portion; and

forming the second gate electrode layer over the cap.

13. A method for forming a semiconductor device comprising:

providing a semiconductor substrate having a first portion and a second portion;

forming a first dielectric over the first portion of the semiconductor substrate, wherein the first dielectric has a high dielectric constant;

forming a second dielectric over the second portion of the semiconductor substrate;

forming a cap over the second dielectric, wherein the cap comprises silicon;

forming a first gate electrode over the first dielectric, wherein the first gate electrode comprises metal; and

forming a second gate electrode over the cap but not over the first gate electrode, wherein the second gate electrode comprises silicon.

14. The method of claim 13 , wherein forming the first dielectric and forming the second dielectric comprise forming different dielectric materials.

15. The method of claim 13 , wherein forming the first dielectric and forming the second dielectric comprise forming the same dielectric material.

16. The method of claim 13 , wherein forming the first dielectric comprises forming a gate dielectric.

17. The method of claim 13 , wherein forming the first dielectric, wherein the first dielectric has the high dielectric constant comprise forming the first dielectric, wherein the first dielectric has a dielectric constant greater than approximately 4.

18. A semiconductor device comprising:

a semiconductor substrate comprising a first portion and a second portion;

a first dielectric layer over the first portion;

a cap over the first dielectric layer;

a first gate electrode layer over the cap;

a second dielectric layer over the second portion; and

a second gate electrode layer over the second dielectric layer wherein the first gate electrode layer and the second gate electrode layer do not overlie each other.

19. The semiconductor device of claim 18 , wherein

the cap comprises polysilicon;

the first gate electrode layer is different than the second gate electrode layer; and

and the first dielectric layer is different than the second dielectric layer.

20. The semiconductor device of claim 19 , wherein the second dielectric layer has a dielectric constant greater than approximately 4.

21. The method of claim 13 , wherein:

the forming the first gate electrode further comprises forming the first gate electrode after forming the cap; and

the forming the second gate electrode further comprises forming the second gate electrode after forming the first gate electrode.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2004
From: MIN, BYOUNG W.; CAVE, NIGEL G.; KOLAGUNTA, VENKAT R.; ZIA, OMAR; GOKTEPELI, SINAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015644/0197 →