IP Library Granted Patent US 7,164,566
Granted Patent B2
US 7,164,566 · App. 10/805,119 · Granted Jan 16, 2007

Electrostatic discharge protection device and method therefore

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Quick Facts
Patent No.
US 7,164,566
App. No.
10/805,119
Granted
Jan 16, 2007
Kind
B2
Abstract

Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.

Claims (45)

1. An electrostatic discharge (ESD) protection device having a first terminal and a second terminal, the device comprising:

a transistor having a collector coupled to the first terminal of the ESD protection device a base and an emitter coupled to the second terminal of the ESD protection device, said transistor having a base region of a first type;

a zener diode having a first terminal coupled to said collector of said transistor and a second terminal coupled said base of said transistor wherein said zener diode breaks down in an ESD event providing impact ionization current to said base region of said transistor;

a first region of said first type formed in said base region, said first region configured to redistribute current away from a surface of said base region to increase a peak current handled by the ESD protection device; and

a second region of said first type formed in said first region, said second region coupling to the second terminal of the ESD protection device.

2. The device as recited in claim 1 further including:

a substrate of said first type;

an epitaxial layer of a second type; and

an isolation region formed in said epitaxial layer for defining an active area of the ESD protection device, said active area corresponding to said epitaxial layer interior to said isolation region.

3. The device as recited in claim 2 wherein said isolation region is of said first type.

4. The device as recited in claim 3 wherein said isolation region comprises a deep trench.

5. The device as recited in claim 2 further including:

an emitter region of said second type formed in said base region, said emitter region coupling to the second terminal of the ESD protection device;

said first region being spaced a predetermined distance from said emitter region; and said base region formed in said active area;

wherein a depth of said first region into said base region is greater than a depth of said second region.

6. The device as recited in claim 5 wherein said doping concentration of said second region is greater than a doping concentration of said first region.

7. The device as recited in claim 6 wherein said first region is formed in a ring shape and wherein said emitter region is centrally located interior to said ring shape of said first region and wherein a depth of said first region in said base region is greater than a depth of said emitter region.

8. The device as recited in claim 7 further including:

a buried layer of said second type underlying a portion of said active area; and

a third region of said second type spaced a predetermined distance from said base region, said third region coupling to said buried layer and the first terminal of the ESD protection device.

9. The device as recited in claim 8 wherein said third region is formed in a ring shape and wherein said base region is located interior to said ring shape of said third region.

10. The device as recited in claim 9 further including a fourth region of said first type formed overlying a boundary between said base region and said epitaxial layer.

11. The device as recited in claim 10 wherein said zener diode comprises said fourth region, said epitaxial layer, and said third region.

12. A method of protecting a semiconductor device from an electrostatic discharge comprising the steps of:

breaking down a zener diode during an electrostatic discharge (ESD) event such that an impact ionization current is generated; and

enabling a transistor with said impact ionization current to dissipate said ESD event before the semiconductor device is damaged wherein said impact ionization current is distributed uniformly through a base region of said transistor via a first region formed in said base region to prevent current crowding at a surface of said base region, the first region having a doping concentration greater than a doping concentration of said base region and having a second region formed in said first region, the second region having a doping concentration greater than said doing concentration of said first region.

13. The method as recited in claim 12 further including a step of distributing said ionization current below a surface of said transistor.

14. The method as recited in claim 12 further including a step of reducing a resistance in a path of said impact ionization current.

15. An electrostatic discharge (ESD) device having a first terminal and a second terminal, the ESD device comprising:

a substrate of a first type;

an epitaxial layer of a second type overlying said substrate;

an isolation region formed in said epitaxial layer to define an active area of the ESD device;

a base region of said first type formed in said epitaxial layer interior to said isolation region;

an emitter region of said second type formed in said base region, said emitter region coupled to the second terminal;

a first region of said first type formed in said base region adjacent to said emitter region wherein said first region has a depth greater than 30% of a depth of said base region and wherein said first region is coupled to said emitter region;

a second region of said first type formed in said first region; and

a zener diode having a first terminal coupled to said epitaxial layer interior to said isolation region and a second terminal coupled to said base region.

16. The ESD device as recited in claim 15 wherein said first region has a higher doping concentration than said base region and wherein said second region has a higher doping concentration than said first region.

17. The ESD device as recited in claim 16 further including:

a buried layer underlying said base region;

a third region of said second type formed in said epitaxial layer interior to said isolation region, said third region extending from a surface of said epitaxial layer to said buried layer; and

a fourth region of said second type formed in said third region, said fourth region coupling to the first terminal of the ESD device.

18. The ESD device as recited in claim 17 further including a fifth region of said first type overlying a boundary of between said base region and said epitaxial region interior to said isolation region.

19. The ESD device as recited in claim 18 wherein said fifth region and said third region are spaced a predetermined distance apart and wherein said zener diode comprises said third region, said epitaxial region interior to said isolation region, and said fifth region.

20. The ESD device as recited in claim 19 wherein the first terminal of the ESD device couples to circuitry of an integrated circuit to be protected and wherein said the second terminal of the ESD device couples to ground.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2004
From: XU, HONGZHONG; BAUMERT, BETH A.; IDA, RICHARD T.
To: MOTOROLA, INC.
Reel/Frame 015121/0097 →