Method for maintaining topographical uniformity of a semiconductor memory array
View Patent ↗A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.
1. A method of forming a semiconductor device comprising:
defining a plurality of active areas on a semiconductor substrate;
forming a plurality of gate stacks on the plurality of active areas;
forming a ring over the substrate and around the plurality of gate stacks, the ring having a composition and height substantially the same as a composition and height of the plurality of gate stacks;
depositing an insulating layer over the plurality of gate stacks and the ring; and
planarizing the insulating layer.
2. The method of claim 1 , wherein forming the plurality of gate stacks further comprises forming each of the plurality of gate stacks with a control gate and a floating gate.
3. The method of claim 1 , wherein forming the plurality of active areas further comprises forming a plurality of parallel longitudinal active areas, each of the longitudinal active areas being surrounded by a trench.
4. The method of claim 1 , wherein forming the plurality of gate stacks further comprises forming each of a plurality of gate stacks with a discrete charge storage layer.
5. The method of claim 1 , wherein forming the ring further comprises forming the ring having a width between 0.5 and 2 microns wide.
6. A method for providing a semiconductor device, the method comprising:
providing an active area formed in a semiconductor substrate;
providing a plurality of non-volatile memory cells formed in the active area, each of the plurality of non-volatile memory cells having a source, a drain, and a gate stack, wherein the gate stack comprises a first oxide layer formed over the active area, a discrete charge storage layer formed over the first oxide layer, a second oxide layer formed over the discrete charge storage layer, and a control gate formed over the second oxide layer; and
providing a ring formed around the plurality of memory cells, the ring having a composition and height substantially the same as a composition and height of the gate stack.
7. A method as in claim 6 , wherein the discrete charge storage layer is a floating gate.
8. A method as in claim 6 , wherein the ring is electrically isolated from the plurality of memory cells.
9. A method as in claim 6 , wherein the ring is continuous.
10. A method as in claim 6 , wherein the active area is surrounded by a trench etched into the semiconductor substrate.
11. A method as in claim 6 , further comprising providing an active boundary formed around the memory array, wherein the ring is formed directly over the active boundary.
12. A method as in claim 6 , further comprising providing a nitride spacer formed on a side of the ring.
13. A method as in claim 6 , wherein the first oxide comprises a tunnel oxide and the second oxide comprises an oxide-nitride-oxide (ONO) stack.
14. A method as in claim 6 , wherein the active area comprises a plurality of longitudinal active regions, each of the longitudinal active regions surrounded by trenches.
15. A method as in claim 6 , further comprising providing an insulating layer formed over the plurality of memory cells and over the ring, wherein a chemical mechanical polishing process is used to planarize the insulating layer.
16. A method for providing a semiconductor device, the method comprising:
providing a memory array having a plurality of non-volatile memory cells, each non-volatile memory cell of the plurality of non-volatile memory cells having a gate stack, the gate stack including a control gate and a discrete charge storage layer; and
providing a dummy stack ring formed around the memory array, the dummy stack ring having a composition and height substantially the same as a composition and height of the gate stack.
17. A method as in claim 16 , wherein the dummy stack ring is continuous.
18. A method as in claim 16 , wherein the plurality of non-volatile memory cells is formed on a plurality of parallel longitudinal active regions, each of the longitudinal active regions surrounded by trenches.
19. A method as in claim 16 , wherein the discrete charge storage layer comprises a floating gate.
20. A method as in claim 16 , further comprising providing an insulating layer formed over the plurality of non-volatile memory cells and over the dummy stack ring, wherein a chemical mechanical polishing process is used to planarize the insulating layer.