Prefetch control in a data processing system
View Patent ↗A data processing system ( 10 ) includes an interconnect ( 22 ) where a first interconnect master ( 12 ) and a second interconnect master ( 14 ) are coupled to the interconnect. A shared storage ( 35 ) is coupled to the interconnect for use by the first and second interconnect masters. The data processing system also includes a first control storage circuit ( 60, 64 ) which corresponds to the first interconnect master and a second control storage circuit ( 62, 66 ) which corresponds to the second interconnect master. In one embodiment, prefetch circuitry ( 40 ) is coupled to the first control storage circuit and to the second control storage circuit for selecting one of the first and second control storage circuits based upon which one of the first and second interconnect masters is requesting an access to the shared storage. The prefetch circuitry can then use the selected control storage circuit to determine a prefetch operation triggered by the access to the shared storage.
1. A data processing system, comprising:
interconnect;
a first interconnect master, coupled to the interconnect;
a second interconnect master, coupled to the interconnect;
shared storage, coupled to the interconnect, for use by the first interconnect master and the second interconnect master;
a first control storage circuit which corresponds to the first interconnect master;
a second control storage circuit which corresponds to the second interconnect master; and
prefetch circuitry, coupled to the first control storage circuit and to the second control storage circuit, said prefetch circuitry selects one of the first and second control storage circuits based upon which one of the first and second interconnect masters is requesting an access to the shared storage, and said prefetch circuitry uses the selected control storage circuit to selectively restrict prefetches from the shared storage triggered by the access to the shared storage.
2. The data processing system as in claim 1 , wherein the shared storage is a memory.
3. The data processing system as in claim 2 , wherein the memory is a flash memory.
4. The data processing system as in claim 1 , wherein the data processing system is formed on a single integrated circuit.
5. The data processing system as in claim 1 , wherein the interconnect comprises at least one bus having a bus protocol.
6. The data processing system as in claim 1 , wherein the first interconnect master executes instructions, and wherein the first control storage circuit and the prefetch circuitry selectively restrict prefetches to instruction accesses.
7. The data processing system as in claim 1 , wherein the first interconnect master performs direct memory accesses, and wherein the first control storage circuit and the prefetch circuitry selectively restrict prefetches to data accesses.
8. The data processing system as in claim 1 , wherein the first interconnect master performs debug operations, and wherein the first control storage circuit and the prefetch circuitry selectively restrict prefetches by preventing prefetches.
9. The data processing system as in claim 1 , wherein the first control storage circuit and the prefetch circuitry selectively restrict prefetches by preventing prefetches for non-burst accesses.
10. The data processing system as in claim 1 , wherein the interconnect comprises at least one conductor that identifies which one of the first and second interconnect masters is requesting the access to the shared storage.
11. The data processing system as in claim 1 , wherein the access is a read access.
12. A method for providing prefetch control, the method comprising:
receiving an access request to access storage;
providing a prefetch control storage circuit to store prefetch burst access control information; and
selectively initiating a prefetch to the storage, based upon the burst access control information and whether the access request is a burst access.
13. A method as in claim 12 , further comprising:
providing a first interconnect master; and
providing a second interconnect master;
wherein the step of providing a prefetch control storage circuit comprises selecting, based upon whether the access request is from the first interconnect master or the second interconnect master, one of a plurality of prefetch control storage circuits to provide the burst access control information.
14. A method as in claim 13 , wherein the step of selectively initiating a prefetch to the storage comprises selectively initiating a prefetch to the storage, based upon the burst access control information, based upon whether the access request is a burst access, and based upon whether the access request is an instruction access or a data access.
15. A method as in claim 12 , wherein the access request is a read access request.
16. A method as in claim 12 , wherein the storage comprises flash memory.
17. A method for providing prefetch control in a data processing system, the method comprising:
providing a first interconnect master;
providing a second interconnect master;
receiving an access request to access shared storage;
selecting a prefetch control storage circuit based upon whether the access request is from the first interconnect master or the second interconnect master;
using control information stored in the prefetch storage circuit to control a prefetch operation triggered by the access request to the shared storage, wherein using the control information stored in the prefetch storage circuit to control the prefetch operation triggered by the access request to the shared storage comprises selectively initiating a prefetch to the shared storage based upon whether the access request is a burst access.
18. A method as in claim 17 , wherein the shared storage is a memory.
19. A method for providing prefetch control in a data processing system, the method comprising:
providing a first interconnect master;
providing a second interconnect master;
receiving an access request to access shared storage;
selecting a prefetch control storage circuit based upon whether the access request is from the first interconnect master or the second interconnect master;
using control information stored in the prefetch storage circuit to control a prefetch operation triggered by the access request to the shared storage, wherein using control information stored in the prefetch storage circuit to control a prefetch operation triggered by the access request to the shared storage comprises selectively initiating a prefetch to the shared storage based upon whether the access request is an instruction access or a data access.
20. The data processing system as in claim 19 , wherein the shared storage is a memory.
21. A method for providing prefetch control in a data processing system, the method comprising:
providing a first interconnect master;
providing a second interconnect master;
receiving an access request to access shared storage;
selecting a prefetch control storage circuit based upon whether the access request is from the first interconnect master or the second interconnect master;
using control information stored in the prefetch storage circuit to selectively initiate a prefetch to the shared storage based on at least one access attribute of the access request.
22. The method of claim 21 , wherein the at least one access attribute of the access request comprises whether the access request is an instruction access or a data access.
23. The method of claim 21 , wherein the at least one access attribute of the access request comprises whether the access request is burst access.