Process for forming an electronic device including semiconductor layers having different stresses
View Patent ↗An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
1. A process of forming an electronic device comprising:
providing a workpiece, wherein:
the workpiece includes a first semiconductor layer, an insulating layer, and a base layer;
the insulating layer lies between the first semiconductor layer and the base layer, and
the first semiconductor layer has a first stress, the first stress having a first magnitude and a first type;
forming a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a second stress, the second stress having a second magnitude and a second type;
annealing the workpiece such that the second semiconductor layer has a third stress, the third stress having a third magnitude and a third type, wherein the third magnitude is different than the second magnitude; and
removing at least a portion of the second semiconductor layer to expose a portion of the first semiconductor layer, wherein after removing the at least a portion of the second semiconductor layer, the first semiconductor layer has a fourth stress, the fourth stress having a fourth magnitude and a fourth type, and the fourth type is opposite the second type.
2. The process of claim 1 , wherein forming the second semiconductor layer comprises forming the second semiconductor layer immediately adjacent to the first semiconductor layer.
3. The process of claim 2 , wherein forming the second semiconductor layer comprises selectively forming the second semiconductor layer over only a portion of the first semiconductor layer.
4. The process of claim 1 , wherein annealing the workpiece comprises annealing the workpiece on only a portion of the workpiece.
5. The process of claim 4 , wherein annealing the workpiece on only a portion of the workpiece comprises laser annealing only a portion of the workpiece.
6. The process of claim 1 , wherein annealing the workpiece comprises annealing the workpiece such that:
the first semiconductor layer has a substantially same material composition before and after annealing the workpiece; and
the second semiconductor layer has a substantially same material composition before and after annealing the workpiece.
7. The process of claim 1 , wherein forming the second semiconductor layer comprises epitaxially growing a layer that includes silicon and germanium.
8. The process of claim 1 , wherein the second semiconductor layer has a thickness not greater than approximately 110 nm.
9. The process of claim 1 , wherein the fourth type is tensile.
10. The process of claim 1 , wherein each of the first magnitude and the third magnitude is less than approximately 10 MPa.
11. The process of claim 1 , wherein providing a workpiece further comprises:
providing a workpiece, wherein:
the workpiece includes a third semiconductor layer;
the insulating layer lies between the third semiconductor layer and the base layer,
the third semiconductor has a fourth stress, the fifth stress having a fifth magnitude and a fifth type, and
the fourth magnitude is less than approximately 10 MPa;
forming a fourth semiconductor layer over the third semiconductor layer wherein the fourth semiconductor layer includes a first element;
increasing the concentration of the first element within the third semiconductor layer to form the first semiconductor layer; and
removing the fourth semiconductor layer to expose the first semiconductor layer, wherein the first layer has the first stress.
12. The process of claim 1 , wherein the first semiconductor layer comprises a first semiconductor material and the first semiconductor material has a spatial ordering of a different dimension from monocrystalline silicon when the spatial ordering of each of the first semiconductor material and the monocrystalline silicon is measured at a substantially same temperature and under a substantially same combination of externally applied forces.
13. The process of claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise different semiconductor element compositions.
14. The process of claim 1 , wherein the first semiconductor layer has a first semiconductor element composition, and the second semiconductor layer has a second semiconductor element composition different from the first semiconductor element composition.
15. The process claims of claim 1 , wherein the first semiconductor layer comprises monocrystalline silicon, and the second semiconductor layer comprises Si (x) Ge (1−x) , wherein x is in a range of approximately 0.1 to less than 1.0.
16. The process claims of claim 1 , wherein the first semiconductor layer comprises Si (x) Ge (1−x) , wherein x is in a range of approximately 0.1 to less than 1.0, and the second semiconductor layer comprises monocrystalline silicon.
17. The process claims of claim 1 , wherein the first semiconductor layer comprises Si (x) C (1−x) , wherein x is in a range of approximately 0.1 to less than 1.0.
18. The process claims of claim 1 , wherein the second semiconductor layer comprises Si (x) C (1−x) , wherein x is in a range of approximately 0.1 to less than 1.0.
19. The process of claim 11 , wherein the first semiconductor layer has a first semiconductor element composition, the third semiconductor layer has a second semiconductor element composition different from the first semiconductor element composition, and the fourth semiconductor layer has a third semiconductor element composition different from each of the first and second semiconductor element compositions.
20. The process of claim 11 , wherein providing the workpiece including the third semiconductor layer, forming the fourth semiconductor layer, increasing the concentration of the first element within the third semiconductor layer to form the first semiconductor layer; and removing the fourth semiconductor layer are performed before forming the second semiconductor layer.