IP Library Granted Patent US 6,856,173
Granted Patent B1
US 6,856,173 · App. 10/656,051 · Granted Feb 15, 2005

Multiplexing of digital signals at multiple supply voltages in an integrated circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,856,173
App. No.
10/656,051
Granted
Feb 15, 2005
Kind
B1
Abstract

An integrated circuit ( 10 ) includes a multiple voltage digital multiplexer circuit ( 30 ) for multiplexing digital signals provided at different supply voltage levels. In one form, the multiplexer ( 30 ) includes an analog multiplexer ( 32 ) for receiving the digital signals, a level shifter ( 40 ) coupled to the output of the analog multiplexer ( 32 ), and a supply voltage multiplexer ( 34 ) for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed. A control circuit ( 38, 39 ) is used to control the input selection of the analog multiplexer ( 32 ) as well as the supply voltage multiplexer ( 34 ) for providing the correct supply voltage to the level shifter ( 40 ). This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC ( 10 ).

Claims (71)

1. An integrated circuit die comprising:

a multiplexer having a first terminal coupled to a first digital signal line that when at a first state is at a voltage dependent upon a first power supply voltage, a second terminal coupled to a second digital signal line that when at a first state is at voltage dependent upon a second power supply voltage, and a third terminal, the multiplexer receiving a control signal, the multiplexer coupling its third terminal to one of at least its first terminal or its second terminal based upon the control signal;

a level shifter having a first signal terminal coupled to the third terminal of the multiplexer, a second signal terminal coupled to a third circuit, and a voltage supply terminal; and

a second multiplexer having a first terminal coupled to receive a voltage dependent upon the first power supply voltage, a second terminal coupled to receive a voltage dependent upon the second power supply voltage, and a third terminal coupled to the voltage supply terminal of the level shifter, the second multiplexer receiving a second control signal, wherein the second multiplexer provides at its third terminal a voltage of one of at least a voltage of its first terminal or a voltage of its second terminal based upon the second control signal.

2. The integrated circuit die of claim 1 wherein the third circuit includes a pad of the integrated circuit die.

3. The integrated circuit die of claim 1 wherein the first control signal and the second control signal are dependent upon a common control signal.

4. The integrated circuit die of claim 3 wherein the first control signal and the second control signal are dependent upon a common control signal such that when the multiplexer couples its third terminal to its first terminal, the second multiplexer provides at its third terminal the voltage of its first terminal and; such that when the multiplexer couples its third terminal to its second terminal, the second multiplexer provides at its third terminal the voltage of its second terminal.

5. The integrated circuit die of claim 1 wherein the level shifter includes a second supply terminal coupled to receive a third voltage that is different from a voltage provided to the supply terminal of the level shifter.

6. The integrated circuit die of claim 5 wherein the third circuit is powered at the third voltage.

7. The integrated circuit die of claim 5 wherein the third voltage is higher than the voltage provided to the supply terminal of the level shifter.

8. The integrated circuit die of claim 1 further comprising:

a first circuit having a terminal coupled to the first digital signal line, the first circuit being powered at the first power supply voltage; and

a second circuit having a terminal coupled to the second digital signal line, the second circuit being powered at the second power supply voltage.

9. The integrated circuit die of claim 8 wherein the first circuit includes a digital signal processor core and the second circuit includes an application processor core.

10. The integrated circuit die of claim 1 further comprising:

a control register for storing a control value, the control signal and the second control signal being dependent upon the control value.

11. The integrated circuit die of claim 10 further comprising:

a second level shifter having a signal input coupled to an output of the control register to receive a signal indicative of the control value, wherein the second level shifter includes a signal output, wherein the control signal and the second control signal are dependent upon the output of the second level shifter.

12. The integrated circuit of die of claim 1 wherein the multiplexer and the second multiplexer each include a power supply terminal for receiving a third power supply voltage.

13. The integrated circuit die of claim 12 wherein the third circuit receives the third power supply voltage, wherein the level shifter includes a second voltage supply terminal coupled to receive the third power supply voltage.

14. The integrated circuit of claim 1 wherein the first multiplexer and the second multiplexer are characterized as being analog multiplexers.

15. The integrated circuit of claim 14 wherein the first multiplexer includes a pass gate.

16. The integrated circuit of claim 1 wherein:

the first signal terminal of the level shifter is an input signal terminal of the level shifter.

17. The integrated circuit of claim 1 further comprising:

a third multiplexer having a first terminal coupled to a third digital signal line that when at a first state is at a voltage dependent upon; the first power supply voltage, a second terminal coupled to a fourth digital signal line that when at a first state is at a voltage dependent upon the second power supply voltage, and a third terminal, the third multiplexer receiving a third control signal, the third multiplexer coupling the third terminal to one of at least its first terminal or its second terminal based upon the third control signal; and

a second level shifter having a first signal terminal coupled the third terminal of the second multiplexer and a voltage supply terminal coupled to the third terminal of the second multiplexer.

18. The integrated circuit die of claim 17 wherein the first control signal, the second control signal, and the third control signal are dependent upon a common control signal.

19. The integrated circuit of claim 17 wherein:

the second level shifter includes a second signal terminal coupled to the third circuit;

the first signal terminal of the level shifter is an input signal terminal;

the second signal terminal of the level shifter is an output signal terminal;

the first signal terminal of the second level shifter is an output signal terminal; and

the second signal terminal of the second level shifter is an input signal terminal.

20. The integrated circuit of claim 19 wherein the third circuit includes an input/output pad of the integrated circuit die.

21. The integrated circuit of claim 17 wherein:

the first digital signal line is an output signal line of a first circuit;

the third signal line is an input signal line of the first circuit;

the second digital signal line is an output signal line of a second circuit; and

the fourth signal line is an input signal line of the second circuit.

22. A wireless device including the integrated circuit die of claim 1 .

23. The wireless device of claim 22 wherein the wireless device performs voice and/or data transmitting and/or receiving functions.

24. A method of multiplexing digital signal lines comprising:

selecting one of at least a first digital signal line and a second digital signal line to couple to a signal terminal of a level shifter for conveying a digital signal between the level shifter and the one of the at least first digital signal line and the second digital signal line;

powering a first circuit coupled to the first digital signal line at a first power supply voltage, wherein when the first digital signal line is at a first state, the first digital signal line is at a voltage dependent upon the first power supply voltage;

powering a second circuit coupled to the second digital signal line at a second power supply voltage, wherein when the second digital signal line is at a first state, the second digital signal line is at a voltage dependent upon the second power supply voltage; and

selecting one of at least a first voltage and a second voltage to supply to a supply voltage terminal of the level shifter, wherein the first voltage is dependent upon the first power supply voltage and the second voltage is dependent upon the second power supply voltage, wherein the first voltage is selected when the first digital signal line is selected to be coupled to the signal terminal and the second voltage is selected when the second digital signal line is selected to be coupled to a signal terminal.

25. The method of claim 24 further comprising:

adjusting the voltage powering the first circuit to power the first circuit at a third power supply voltage, wherein the adjusting further includes supplying a third voltage dependent upon the third power supply voltage to the supply voltage terminal of the level shifter when the first digital signal line is selected.

26. The method of claim 24 wherein the selecting one of at least a first digital signal line and a second digital signal line and the selecting one of at least a first voltage and a second voltage further include writing to a control register a control value indicative of one of at least the first digital signal line and the second digital signal line.

27. The method of claim 24 further comprising:

providing by a first circuit a digital signal on the first digital signal line to the signal terminal of the level shifter when the first digital signal line is selected to be coupled to the signal terminal of the level shifter.

28. The method of claim 27 further comprising:

level shifting by the level shifter the digital signal received from the, first digital signal line when the first digital signal line is selected to be coupled to the signal terminal of the level shifter.

29. The method of claim 27 further comprising:

providing the digital signal from the level shifter to a pad of the integrated circuit.

30. The method of claim 24 further comprising:

receiving by a first circuit a digital signal on a first digital signal line when the first digital signal line is selected to be coupled to the signal terminal of the level shifter.

31. An integrated circuit die comprising:

a first digital signal line coupled to a first circuit receiving a first power supply voltage;

a second digital signal line coupled to a second circuit receiving a second power supply voltage;

a level shifter having a signal terminal and a supply voltage terminal;

means for selecting one of at least the first digital signal line and the second digital signal line to be coupled to the signal terminal of the level shifter; and

means for selecting one of at least a first voltage dependent upon the first power supply voltage and a second voltage dependent upon the second power supply voltage to supply the supply voltage terminal, wherein the first voltage is selected when the first digital signal line is selected to be coupled to the signal terminal of the level shifter and the second voltage is selected when the second digital signal line is selected to be coupled to the signal terminal of the level shifter.

32. The integrated circuit of claim 31 wherein the first digital signal line is an output signal line of the first circuit and the second digital signal line is an output signal line of the second circuit.

33. The integrated circuit die of claim 31 further comprising:

a third digital signal line coupled to the first circuit;

a forth digital signal line coupled to the second circuit;

a second level shifter having a signal terminal and a supply voltage terminal; and

means for selecting one of at least the third digital signal line and the fourth digital signal line to be coupled to the signal terminal of the second level shifter, wherein the third digital signal line is selected when the first voltage is selected and the fourth digital signal line is selected when the second voltage is selected;

wherein the first voltage is supplied to the supply voltage terminal of the second level shifter when the first voltage is selected and the second voltage is supplied to the supply voltage terminal of the second level shifter when the second voltage is selected.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2004
From: CHUN, CHRISTOPHER K.
To: MOTOROLA, INC.
Reel/Frame 015261/0857 →