IP Library Granted Patent US 6,897,562
Granted Patent B2
US 6,897,562 · App. 10/411,744 · Granted May 24, 2005

Electronic component and method of manufacturing same

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Quick Facts
Patent No.
US 6,897,562
App. No.
10/411,744
Granted
May 24, 2005
Kind
B2
Abstract

An electronic component includes an organic interposer ( 160, 460, 560, 660, 760, 860, 960 ), a semiconductor chip ( 220 ) mounted over the organic interposer, copper pads ( 250, 751, 851 ) under the organic interposer, a solder attachment ( 110, 510, 610, 910 ) between certain ones of the copper pads, and solder interconnects ( 120, 420 ) between certain other ones of the copper pads and located around an outer perimeter ( 111, 511, 911 ) of the solder attachment. The solder attachment is placed at locations within the electronic component that experience the greatest stress, which may include, for example, locations adjacent to at least a portion of a perimeter ( 221 ) of the semiconductor chip. In one embodiment, a surface area of the solder attachment is larger than a surface area of each one of the solder interconnects. In the same or another embodiment, the electronic component includes multiple solder attachments.

Claims (70)

1. An electronic component comprising:

an organic interposer comprising a first surface, a second surface, and a copper pad at the second surface;

a semiconductor chip mounted over the first surface of the organic interposer;

a solder attachment under the second surface of the organic interposer and under the copper pad; and

solder interconnects under the second surface of the organic interposer and located at least outside a perimeter of the solder attachment,

wherein:

the solder interconnects have a pitch no treater than approximately one millimeter; and

the solder attachment and the copper pad are located adjacent to a perimeter of the semiconductor chip.

2. The electronic component of claim 1 wherein:

the solder attachment has a surface area larger than a surface area of each of the solder interconnects.

3. The electronic component of claim 1 wherein:

the solder interconnects are arranged in multiple rows and comprise at least one hundred solder interconnects.

4. The electronic component of claim 1 wherein:

the solder interconnects are arranged in a single line outside the perimeter of the semiconductor chip and comprise fewer than one hundred solder interconnects.

5. The electronic component of claim 1 wherein:

the solder interconnects are located inside and outside the perimeter of the semiconductor chip.

6. The electronic component of claim 1 wherein:

the solder interconnects are located only outside the perimeter of the semiconductor chip.

7. The electronic component of claim 1 further comprising:

multiple copper pads, including the copper pad, at the second surface of the organic interposer; and

multiple solder attachments, including the solder attachment, at the second surface of the organic interposer,

wherein:

no more than one of the multiple solder attachments is located underneath any one of the multiple copper pads; and

an aggregate perimeter around the multiple copper pads and the multiple solder attachments is adjacent to the perimeter of the semiconductor chip.

8. The electronic component of claim 7 wherein:

the multiple copper pads comprise four copper pads, each one located adjacent to a different corner of the perimeter of the semiconductor chip; and

the multiple solder attachments comprise four solder attachments, each one located adjacent to a different corner of the perimeter of the semiconductor chip.

9. The electronic component of claim 8 wherein:

the multiple solder attachments are symmetric underneath the organic interposer.

10. The electronic component of claim 8 wherein:

the solder interconnects are located only outside the aggregate perimeter of the multiple copper pads and the multiple solder attachments.

11. An electronic component comprising:

an organic interposer comprising a first surface, a second surface, and a copper pad at the second surface;

a semiconductor chip, mounted over the first surface of the organic interposer;

a solder attachment under the second surface of the organic interposer and under the copper pad;

solder interconnects under the second surface of the organic interposer and located at least outside a perimeter of the solder attachment;

multiple copper pads, including the copper pad, at the second surface of the organic interposer; and

multiple solder attachments, including the solder attachment, at the second surface of the organic interposer,

wherein:

the solder attachment and the copper pad are located adjacent to a perimeter of the semiconductor chip;

no more than one of the multiple solder attachments is located underneath any one of the multiple copper pads;

an aggregate perimeter around the multiple copper pads and the multiple solder attachments is adjacent to the perimeter of the semiconductor chip;

the multiple copper pads comprise eight copper pads, each one of the eight copper pads located adjacent to a different corner or a different side of the perimeter of the semiconductor chip; and

the multiple solder attachments comprise eight solder attachments, each one of the eight solder attachments located adjacent to a different corner or a different side of the perimeter of the semiconductor chip.

12. The electronic component of claim 11 wherein:

the multiple solder attachments are symmetric underneath the organic interposer.

13. The electronic component of claim 11 wherein:

the solder interconnects are located inside and outside the aggregate perimeter of the multiple copper pads and the multiple solder attachments.

14. The electronic component of claim 1 further comprising:

multiple copper pads, including the copper pad, at the second surface of the organic interposer;

wherein:

at least one of the multiple copper pads has underneath it more than one of the solder interconnects; and

an aggregate perimeter around the multiple copper pads is adjacent to the perimeter of the semiconductor chip.

15. The electronic component of claim 14 wherein:

the multiple copper pads comprise eight copper pads, each one of the eight copper pads located adjacent to a different corner or a different side of the perimeter of the semiconductor chip.

16. The electronic component of claim 15 wherein:

the multiple copper pads are symmetric underneath the organic interposer.

17. The electronic component of claim 15 wherein:

the solder interconnects are located inside and outside the aggregate perimeter of the multiple copper pads.

18. The electronic component of claim 1 wherein:

the electronic component comprises a single solder attachment consisting of the solder attachment;

an aggregate perimeter around the copper pad and the single solder attachment is adjacent to the perimeter of the semiconductor chip; and

the solder interconnects are located only outside the perimeter of the semiconductor chip.

19. The electronic component of claim 1 wherein:

the electronic component comprises a single solder attachment having an outer perimeter and an inner perimeter; and

the single solder attachment is adjacent to all of the perimeter of the semiconductor chip.

20. The electronic component of claim 19 wherein:

the solder interconnects are located inside the inner perimeter of the single solder attachment and outside the outer perimeter of the single solder attachment.

21. The electronic component of claim 11 wherein:

the solder interconnects have a pitch no greater than approximately one millimeter.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →