IP Library Granted Patent US 7,432,754
Granted Patent B2
US 7,432,754 · App. 11/460,349 · Granted Oct 7, 2008

Voltage control circuit having a power switch

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Quick Facts
Patent No.
US 7,432,754
App. No.
11/460,349
Granted
Oct 7, 2008
Kind
B2
Abstract

A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Claims (62)

1. A voltage control circuit comprising:

a first voltage supply terminal for receiving a first voltage;

a second voltage supply terminal for receiving a second voltage, wherein the second voltage is different from the first voltage;

a control logic circuit having an enable terminal for receiving an enable signal;

a first driver coupled to the first voltage supply terminal and an external node;

a second driver coupled to the second voltage supply terminal and the external node;

a first transistor having a first conducting terminal, a second conducting terminal, and a control terminal, wherein the first conducting terminal of the first transistor is coupled to the first voltage supply terminal, the control terminal of the first transistor is coupled to receive a first control signal from the control logic circuit;

a second transistor having a first conducting terminal, a second conducting terminal, and a control terminal, wherein the first conducting terminal of the second transistor is coupled to the second conducting terminal of the first transistor, and wherein the control terminal of the second transistor is coupled to receive a second control signal from the control logic circuit;

a third transistor having a first conducting terminal, a second conducting terminal, and a control terminal, wherein the first conducting terminal of the third transistor is coupled to the second voltage supply terminal and wherein the control terminal of the third transistor is coupled to receive a third control signal from the control logic circuit; and

a fourth transistor having a first conducting terminal, a second conducting terminal, and a control terminal, wherein the first conducting terminal of the fourth transistor is coupled to the second conducting terminal of the third transistor, wherein the control terminal of the fourth transistor is coupled to receive a fourth control signal from the control logic circuit, and wherein the second conducting terminal of the second transistor is further coupled to the first conducting terminal of the fourth transistor, wherein in response to a first value of the enable signal the second voltage is provided to the second driver as a result of the control logic circuit turning off the first transistor and the second transistor and the control logic circuit turning on the third transistor and the fourth transistor and wherein in response to a second value of the enable signal the first voltage is provided to the second driver as a result of the control logic circuit turning on the first transistor, the second transistor, the fourth transistor, and the control logic turning off the third transistor.

2. The voltage control circuit of claim 1 , wherein:

the first transistor further comprises bulk region, wherein the first conducting terminal of the first transistor is coupled to the bulk region of the first transistor;

the second transistor further comprises a bulk region, wherein the second conducting terminal of the second transistor is coupled to the bulk region of the second transistor;

the third transistor further comprises a bulk region, wherein the second conducting terminal of the third transistor is coupled to the bulk region of the third transistor; and

the fourth transistor further comprises a bulk region, wherein the second conducting terminal of the fourth transistor is coupled to the bulk region of the fourth transistor.

3. The voltage control circuit of claim 1 , wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a p-channel type transistor.

4. The voltage control circuit of claim 1 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are part of a power switch.

5. The voltage control circuit of claim 1 wherein the external node comprises a bonding pad.

6. The voltage control circuit of claim 1 , wherein the first voltage is greater than the second voltage.

7. A voltage control circuit comprising:

a first driver coupled to a first voltage supply terminal for receiving a first voltage, wherein the first driver is further coupled to an external node;

a power switch coupled to the first voltage supply terminal, a second voltage supply terminal for receiving a second voltage, wherein the second voltage is different from the first voltage, and an enable terminal for receiving an enable signal, wherein the power switch further comprises:

a first transistor having a first conducting terminal, a second conducting terminal, and a first bulk region, wherein:

the first conducting terminal is coupled to the first voltage supply terminal, and

the first conducting terminal is coupled to the first bulk region;

a second transistor having a third conducting terminal, a fourth conducting terminal and a second bulk region, wherein:

the third conducting terminal is coupled to the second conducting terminal of the first transistor;

the fourth conducting terminal is coupled to the second bulk region; and

the fourth conducting terminal is coupled to a node;

a third transistor having a fifth conducting terminal, a sixth conducting terminal, and a third bulk region, wherein:

the fifth conducting terminal is coupled to the second voltage supply terminal;

the sixth conducting terminal is coupled to the third bulk region; and

the sixth conducting terminal is coupled to the node; and

a fourth transistor having a seventh conducting terminal, an eighth conducting terminal, and a fourth bulk region, wherein:

the seventh conducting terminal is coupled to the node; and

the seventh conducting terminal is coupled to the fourth bulk region; and

a second driver coupled to the enable terminal and the eighth conducting terminal of the fourth transistor of the power switch, wherein the second driver is further coupled to the external node, and wherein when the enable terminal receives a first value corresponding to the enable signal, the power switch couples the second voltage to the second driver via the second voltage supply terminal.

8. The voltage control circuit of claim 7 , wherein when the enable terminal receives a second value corresponding to the enable signal, wherein the second value is different form the first value, the power switch couples the first voltage to the second driver via the first voltage supply terminal, wherein the first value corresponds to a low value and the second value corresponds to a high value.

9. The voltage control circuit of claim 7 , wherein the external node comprises a bonding pad.

10. The voltage control circuit of claim 7 , wherein the first voltage is greater than the second voltage.

11. A voltage control circuit comprising:

a first driver coupled to a first voltage supply terminal for receiving a first voltage, wherein the first driver is further coupled to an external node;

a power switch coupled to the first voltage supply terminal, a second voltage supply terminal for receiving a second voltage, wherein the second voltage is different from the first voltage, and an enable terminal for receiving an enable signal;

a control logic circuit for receiving the enable signal and for generating control signals for controlling at least a subset of the functionality of the power switch; and

a second driver coupled to the enable terminal, wherein the second driver is further coupled to the external node, and wherein when the enable terminal receives a first value corresponding to the enable signal, the power switch couples the second voltage to the second driver via the second voltage supply terminal, wherein when the enable terminal receives a second value corresponding to the enable signal, wherein the second value is different form the first value, the power switch couples the first voltage to the second driver via the first voltage supply terminal,

wherein the power switch further comprises:

a first transistor having a first conducting terminal, a second conducting terminal, and a first bulk region, wherein:

the first conducting terminal is coupled to the first voltage supply terminal, and

the first conducting terminal is coupled to the first bulk region;

a second transistor having a third conducting terminal, a fourth conducting terminal and a second bulk region, wherein:

the third conducting terminal is coupled to the second conducting terminal of the first transistor;

the fourth conducting terminal is coupled to the second bulk region; and

the fourth conducting terminal is coupled to a node;

a third transistor having a fifth conducting terminal, a sixth conducting terminal, and a third bulk region, wherein:

the fifth conducting terminal is coupled to the second voltage supply terminal;

the sixth conducting terminal is coupled to the third bulk region; and

the sixth conducting terminal is coupled to the node; and

a fourth transistor having a seventh conducting terminal, an eighth conducting terminal, and a fourth bulk region, wherein:

the seventh conducting terminal is coupled to the node; and the seventh conducting terminal is coupled to the fourth bulk region.

12. The voltage control circuit of claim 11 , wherein the first transistor further comprises a control terminal, the second transistor further comprises a control terminal, the third transistor further comprises a control terminal, and the fourth transistor further comprises a control terminal and wherein a first one of the control signals is coupled to the control terminal of the first transistor, a second one of the control signals is coupled to the control terminal of the second transistor, a third one of the control signals is coupled to the control terminal of the third transistor, and a fourth one of the control signals is coupled to the control terminal of the fourth transistor.

13. The voltage control circuit of claim 11 , wherein the external node comprises a bonding pad.

14. The voltage control circuit of claim 11 , wherein the first voltage is greater than the second voltage.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 12, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2006
From: KASE, KIYOSHI; TRAN, DZUNG T.
To: FREESCALE SEMICONDUCTOR, INC.
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