System and method for monitoring clock signal in an integrated circuit
View Patent ↗A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.
1. A clock monitor system for monitoring an input clock signal to an integrated circuit(IC), wherein the input clock signal switches alternatively between a first logic level and a second logic level, the clock monitor system comprising:
a clock failure detection circuit that generates a control signal based on an input clock signal switching; and
a delay circuit connected to the clock failure detection circuit that provides a clock status signal to the IC based on the control signal after a pre-determined number of input clock cycles, wherein the clock status signal indicates a failure of the input clock signal; and
wherein the clock failure detection circuit comprises:
a plurality of transistors that monitor the input clock signal, wherein at least one of the plurality of transistors is in an OFF state during a first time slot, and wherein each of the plurality of transistors is in an ON state during a second time slot;
an energy storage element connected to the plurality of transistors that charges during the second time slot and discharges during the first time slot; and
an output circuit connected to the energy storage element that generates the control signal based on a voltage level of the energy storage element, wherein the control signal is provided as an input to the delay circuit.
2. The clock monitor system for monitoring the input clock signal of claim 1 , wherein the storage element comprises a capacitor.
3. The clock monitor system for monitoring the input clock signal of claim 1 , wherein the clock failure detection circuit further comprises:
one or more discharge paths connected in parallel to the energy storage element, wherein the one or more discharge path discharge the storage element during the first time slot, and wherein a discharge path of the one or more discharge path is selected based on a frequency range of the input clock signal; and
one or more delay elements connected to the plurality of transistors that apply a distinct phase shifted input clock signal to at least one of the plurality of transistors.
4. The clock monitor system for monitoring the input clock signal of claim 3 , wherein each of the one or more discharge paths comprises one or more transistors.
5. The clock monitor system for monitoring the input clock signal of claim 3 , wherein each of the one or more discharge paths comprises one or more resistors.
6. The clock monitor system for monitoring the input clock signal of claim 3 , wherein the output circuit changes the control signal when the voltage level of the storage element exceeds a threshold voltage.
7. The clock monitor system for monitoring the input clock signal of claim 3 , wherein the delay circuit comprises one or more flip-flops.
8. The clock monitor system for monitoring the input clock signal of claim 7 , wherein the predetermined number of input clock cycles depends on a number of flip-flops of the one or more flip-flops.
9. A method for monitoring an input clock signal to an Integrated Circuit (IC), wherein the input clock signal switches alternatively between a first logic level and a second logic level, the method comprising the steps of:
generating a control signal based on an input clock signal switching to detect a failure of the input clock signal; and
providing a clock status signal to the IC based on the control signal after a predefined number of input clock cycles, wherein the clock status signal indicates the failure of the input clock signal to the IC; and
wherein the step of generating the control signal comprises:
switching at least one of a plurality of transistors to an OFF state during a first time slot and switching each of the plurality of transistors to an ON state during a second time slot based on the input clock signal switching;
charging an energy storage element during the second time slot and discharging the energy storage element during the first time slot; and
generating the control signal based on a voltage level of the energy storage element, wherein the control signal is used to generate the clock status signal.
10. The method for monitoring the input clock signal of claim 9 , wherein the storage element comprises a capacitor.
11. The method for monitoring the input clock signal of claim 9 , wherein the step of providing the clock status signal comprises the step of:
providing the clock status signal as an output of one or more flip-flops that are responsive to the input clock signal, wherein the predefined input clock cycle depends on a number of flip-flops of the one or more flip-flops.