Contention-free hierarchical bit line in embedded memory and method thereof
View Patent ↗A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The bit line driving circuitry further includes a first select input to receive a first select value, a second select input to receive a second select value, and an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.
1. A memory comprising:
a plurality of lower level bit lines comprising:
a first bit line and a second bit line;
a higher level bit line; and
bit line driving circuitry comprising:
a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines;
a first select input to receive a first select value;
a second select input to receive a second select value, the second select value separate from the first select value;
a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of the first select value;
a second transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the first transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a representation of a first bit line value at the first bit line;
a third transistor comprising a first current-carrying electrode coupled to the higher level bit line, a second current-carrying electrode coupled to a second voltage reference, and a control electrode to receive the representation of the first bit line value;
a fourth transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode, and a control electrode to receive a representation of the second select value;
a fifth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the fourth transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode to receive a representation of a second bit line value at the second bit line;
a sixth transistor comprising a first current-carrying electrode coupled to the higher level bit line, a second current-carrying electrode coupled to the second voltage reference, and a control electrode to receive the representation of the second bit line value; and
an output configured to drive a select one of a first bit value or a second bit value at the higher level bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.
2. The memory of claim 1 , wherein:
the first transistor, the second transistor, the fourth transistor and the fifth transistor are transistors of a first conductivity type; and
the third transistor and the sixth transistor are transistors of a second conductivity type.
3. The memory of claim 1 , wherein:
the representation of the first select value is an inverted representation of the first select value;
the representation of the second select value is an inverted representation of the second select value;
the representation of the first bit line value is an inverted representation of the first bit line value; and
the representation of the second bit line value is an inverted representation of the second bit line value.
4. The memory of claim 1 , further comprising:
a first inverter comprising an input coupled to the first bit line and an output coupled to the control electrode of the second transistor and coupled to the control gate of the third transistor, the output to provide the inverted representation of the first bit line value;
a second inverter comprising an input coupled to the second bit line and an output coupled to the control electrode of the fifth transistor and coupled to the control electrode of the sixth transistor, the output to provide the inverted representation of the second bit line value;
a seventh transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to the first bit line, and a control electrode coupled to the output of the first inverter, wherein the seventh transistor is a transistor of the first conductivity type; and
an eighth transistor comprising a first current-carrying electrode coupled to the first voltage reference, a second current-carrying electrode coupled to the second bit line, and a control electrode coupled to the output of the second inverter, wherein the eighth transistor is a transistor of the first conductivity type.
5. A memory comprising:
a plurality of lower level bit lines;
a higher level bit line; and
bit line driving circuitry comprising:
a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines;
a first select input to receive a first select value;
a second select input to receive a second select value;
a NAND gate comprising a first input coupled to a first bit line of the plurality of lower level bit lines, a second input coupled to a second bit line of the plurality of lower level bit lines, and an output;
a first transistor comprising a first current-carrying electrode coupled to a first voltage reference, a second current-carrying electrode, and a control electrode to receive a control value based on an OR logic operation on a representation of the first select value and a representation of the second select value;
a second transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the first transistor, a second current-carrying electrode coupled to the higher level bit line, and a control electrode coupled to the output of the NAND gate; and
a third transistor comprising a first current-carrying electrode coupled to the second higher level bit line, a second current-carrying electrode coupled to a second voltage reference, and a control electrode coupled to the output of the NAND gate; and
an output configured to drive a select one of a first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.
6. The memory of claim 5 , further comprising:
a NOR gate comprising a first input to receive the first select value, a second input to receive the second select value, and an output coupled to the control electrode of the first transistor.
7. The memory of claim 5 , further comprising:
an OR gate comprising a first input to receive the first select value, a second input to receive the second select value, and an output;
an inverter comprising an input coupled to the output of the OR gate and an output coupled to the control electrode of the first transistor; and
a fourth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the third transistor, a second current-carrying electrode coupled to the second voltage reference, and a control electrode to receive a clock signal, wherein the second current-carrying electrode of the third transistor is coupled to the second voltage reference via the fourth transistor.
8. A memory comprising:
a plurality of lower level bit lines;
a higher level bit line; and
bit line driving circuitry comprising:
a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines;
a first select input to receive a first select value;
a second select input to receive a second select value; an OR gate comprising a first input to receive the first select value, a second input to receive the second select value, and an output;
an AND gate comprising a first input coupled to the output of the OR gate, a second input to receive a clock signal, and an output; and
an output configured to drive a select one of a first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines;
an inverter comprising an input coupled to the output of the AND gate and an output coupled to the control electrode of the first transistor; and
a fourth transistor comprising a first current-carrying electrode coupled to the second current-carrying electrode of the third transistor, a second current-carrying electrode coupled to the second voltage reference, and a control electrode coupled to the output of the AND gate, wherein the second current-carrying electrode of the third transistor is coupled to the second voltage reference via the fourth transistor.