IP Library Granted Patent US 8,035,943
Granted Patent B2
US 8,035,943 · App. 12/377,807 · Granted Oct 11, 2011

Protection circuit apparatus

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Quick Facts
Patent No.
US 8,035,943
App. No.
12/377,807
Granted
Oct 11, 2011
Kind
B2
Abstract

A protection circuit apparatus comprises a retriggerable fuse having an awakened state and a sleep state. The retriggerable fuse has an input and an output and is arranged, when in the awakened state, to selectively prevent a load current from flowing from the input to the output in response to the load current exceeding a first current threshold. An activation circuit is also provided and is arranged to sense the load current being drawn. The activation circuit causes the retriggerable fuse to enter the awakened state from the sleep state when the sensed load current exceeds a second current threshold.

Claims (46)

1. A protection circuit apparatus for protecting a load from an over-current, the apparatus comprising:

a retriggerable fuse comprising a control circuit, the retriggerable fuse having an awakened state and a sleep state, the retriggerable fuse being capable, when in the awakened state, of selectively preventing a load current from flowing from an input to an output thereof in response to the load current exceeding a first current threshold; and

an activation circuit arranged to sense the load current being drawn and cause the retriggerable fuse to enter the awakened state from the sleep state in response to the sensed load current exceeding a second current threshold;

wherein the retriggerable fuse has a current-sense output to provide a current-sense output signal indicative that the load current has been sensed, the activation circuit being arranged with the control circuit to use the current-sense output signal to latch the retriggerable fuse in the awakened state, wherein the current-sense output signal is proportional to the load current;

wherein the retriggerable fuse reverting to the sleep state once the current-sense output signal diminishes below a sustain current level so as to release the latch necessary to maintain the retriggerable fuse in the awakened state.

2. An apparatus as claimed in claim 1 , wherein the load current is drawn when the retriggerable fuse is in the sleep state and the load current is less than the second current threshold.

3. An apparatus as claimed in claim 2 , wherein the load current is drawn through the retriggerable fuse.

4. An apparatus as claimed in claim 3 , wherein the retriggerable fuse comprises another threshold-dependent conduction device, the load current being drawn through the another threshold-dependent conduction device.

5. An apparatus as claimed in claim 1 , wherein the retriggerable fuse is arranged to attempt to release the retriggerable fuse from being latched in the awakened state in response to the retriggerable fuse preventing, when in the awakened state, the load current from flowing from the input to the output of the retriggerable fuse.

6. An apparatus as claimed in claim 5 , wherein the activation circuit is arranged to maintain the retriggerable fuse in the awakened state in response to the sensed load current continuing to exceed the second current threshold.

7. An apparatus as claimed in claim 6 , wherein the retriggerable fuse is a solid-state relay.

8. An apparatus as claimed in claim 1 , wherein the activation circuit comprises a threshold-dependent conduction device for transitioning or maintaining the retriggerable fuse in the awakened state, the threshold-dependent conduction device being responsive to the load current drawn exceeding the second current threshold.

9. An apparatus as claimed in claim 8 , wherein the threshold-dependent conduction device is a transistor.

10. An apparatus as claimed in claim 9 , wherein the transistor is a bipolar transistor.

11. An apparatus as claimed in claim 8 , wherein the threshold-dependent conduction device is a voltage comparator.

12. An apparatus as claimed in claim 1 , further comprising:

a processing resource coupled to the retriggerable fuse and arranged to override prevention of flow of the load current from the input to the output of the retriggerable fuse in response to a stimulus external to the processing resource.

13. A method for protecting a load from an over-current, the method comprising:

detecting that a load current is above a first threshold current;

transitioning a first transistor to an on state when the load current is above the first threshold current;

generating an enable signal via the first transistor when the first transistor is in the on state;

transitioning a retriggerable fuse to an awaken state and a second transistor into an on state in response to the enable signal;

providing the load current to the load through the second transistor when the second transistor is in the on state;

generating a current-sense signal that is proportional to the load current via the second transistor;

detecting that the load current has exceeded an overcurrent threshold based on the current-sense signal;

placing the second transistor in an off state when the load current has exceeded an overcurrent threshold;

ceasing a flow of the load current to the load when the second transistor is in the off state;

transitioning the retriggerable fuse in a sleep state when the load current is below the first current threshold; and

enabling the flow of the load current to the load when the load current is below a sustain current level.

14. The method of claim 13 , further comprising:

placing the first transistor in an off state when the second transistor is in the on state; and

transitioning the first transistor to the on state when the load current is above the overcurrent threshold.

15. The method of claim 13 , further comprising:

maintaining the second transistor in the on state while the current-sense signal is above the sustain current level.

16. The method of claim 13 , further comprising:

maintaining the retriggerable fuse in the awaken state and the second transistor in the off state continue to cease the flow of the load current to the load while the load current is above the overcurrent threshold.

17. A protection circuit apparatus for protecting a load from an over-current, the apparatus comprising:

an activation circuit including a first transistor transitions to an on state and generates an enable signal when a load current is above a first threshold current; and

a retriggerable fuse including:

a second transistor to provide the load current to the load when the second transistor is in an on state, to generate a current-sense signal that is proportional to the load current, to cease providing the load current to the load when the second transistor is in an off state; and

a control circuit in communication with the activation circuit and the second transistor, the control circuit to transition the retriggerable fuse to an awaken state and to transition the second transistor to the on state in response to receiving the enable signal, to maintain the second transistor in the on state while the current-sense signal is above a sustain current level, to detect that the load current has exceeded an overcurrent threshold based on the current-sense signal, to place the second transistor in the off state when the load current has exceeded the overcurrent threshold, to maintain the retriggerable fuse in the awaken state and the second transistor in the off state while the load current has exceeded the overcurrent threshold, and to transition the retriggerable fuse to a sleep state when the load current is below the sustain current level,

wherein the first transistor transitions to an off state in response to the second transistor transitioning to the on state.

18. The protection circuit apparatus of claim 17 , wherein the activation circuit maintains the retriggerable fuse in the awakened state in response to the current-sense signal continuing to exceed the sustain current level.

19. The protection circuit apparatus of claim 17 , further comprising:

a processing resource in communication with the retriggerable fuse, the processing resource overrides ceasing of the flow of the load current to the load through the second transistor in response to an override signal.

20. The protection circuit apparatus of claim 19 , wherein the override signal is external to the processing resource.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0793 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2010
From: TURPIN, PIERRE; REITER, THOMAS JEFFREY
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded May 19, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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